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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2018, 2020 NXP
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* Copyright 2014-2015, Freescale Semiconductor
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*/
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#ifndef _FSL_LAYERSCAPE_CPU_H
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#define _FSL_LAYERSCAPE_CPU_H
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#ifdef CONFIG_FSL_LSCH3
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#define CFG_SYS_FSL_CCSR_BASE 0x00000000
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#define CFG_SYS_FSL_CCSR_SIZE 0x10000000
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#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
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#define CFG_SYS_FSL_QSPI_SIZE1 0x10000000
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#ifndef CONFIG_NXP_LSCH3_2
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#define CFG_SYS_FSL_IFC_BASE1 0x30000000
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#define CFG_SYS_FSL_IFC_SIZE1 0x10000000
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#define CFG_SYS_FSL_IFC_SIZE1_1 0x400000
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#endif
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#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
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#define CFG_SYS_FSL_QSPI_SIZE2 0x100000000
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#ifndef CONFIG_NXP_LSCH3_2
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#define CFG_SYS_FSL_IFC_BASE2 0x500000000
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#define CFG_SYS_FSL_IFC_SIZE2 0x100000000
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#endif
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#define CFG_SYS_FSL_DCSR_BASE 0x700000000
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#define CFG_SYS_FSL_DCSR_SIZE 0x40000000
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#define CFG_SYS_FSL_MC_BASE 0x80c000000
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#define CFG_SYS_FSL_MC_SIZE 0x4000000
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#define CFG_SYS_FSL_NI_BASE 0x810000000
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#define CFG_SYS_FSL_NI_SIZE 0x8000000
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#define CFG_SYS_FSL_QBMAN_BASE 0x818000000
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#define CFG_SYS_FSL_QBMAN_SIZE 0x8000000
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#define CFG_SYS_FSL_QBMAN_SIZE_1 0x4000000
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#ifdef CONFIG_ARCH_LS2080A
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#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000
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#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000
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#define CFG_SYS_PCIE3_PHYS_SIZE 0x200000000
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#define CFG_SYS_PCIE4_PHYS_SIZE 0x200000000
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#else
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#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
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#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
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#ifndef CFG_SYS_PCIE3_PHYS_SIZE
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#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
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#endif
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#define CFG_SYS_PCIE4_PHYS_SIZE 0x800000000
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#define SYS_PCIE5_PHYS_SIZE 0x800000000
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#define SYS_PCIE6_PHYS_SIZE 0x800000000
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#endif
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#define CFG_SYS_FSL_WRIOP1_BASE 0x4300000000
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#define CFG_SYS_FSL_WRIOP1_SIZE 0x100000000
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#define CFG_SYS_FSL_AIOP1_BASE 0x4b00000000
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#define CFG_SYS_FSL_AIOP1_SIZE 0x100000000
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#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
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#define CFG_SYS_FSL_PEBUF_BASE 0x4c00000000
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#else
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#define CFG_SYS_FSL_PEBUF_BASE 0x1c00000000
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#endif
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#define CFG_SYS_FSL_PEBUF_SIZE 0x400000000
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#ifdef CONFIG_NXP_LSCH3_2
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#define CFG_SYS_FSL_DRAM_BASE2 0x2080000000
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#define CFG_SYS_FSL_DRAM_SIZE2 0x1F80000000
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#define CFG_SYS_FSL_DRAM_BASE3 0x6000000000
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#define CFG_SYS_FSL_DRAM_SIZE3 0x2000000000
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#else
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#define CFG_SYS_FSL_DRAM_BASE2 0x8080000000
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#define CFG_SYS_FSL_DRAM_SIZE2 0x7F80000000
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#endif
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#elif defined(CONFIG_FSL_LSCH2)
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#define CFG_SYS_FSL_CCSR_BASE 0x1000000
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#define CFG_SYS_FSL_CCSR_SIZE 0xf000000
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#define CFG_SYS_FSL_DCSR_BASE 0x20000000
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#define CFG_SYS_FSL_DCSR_SIZE 0x4000000
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#define CFG_SYS_FSL_QSPI_BASE 0x40000000
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#define CFG_SYS_FSL_QSPI_SIZE 0x20000000
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#define CFG_SYS_FSL_IFC_BASE 0x60000000
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#define CFG_SYS_FSL_IFC_SIZE 0x20000000
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#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CFG_SYS_FSL_QBMAN_BASE 0x500000000
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#define CFG_SYS_FSL_QBMAN_SIZE 0x10000000
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#define CFG_SYS_FSL_DRAM_BASE2 0x880000000
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#define CFG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
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#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
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#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
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#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
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#define CFG_SYS_FSL_DRAM_BASE3 0x8800000000
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#define CFG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
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#endif
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int fsl_qoriq_core_to_cluster(unsigned int core);
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u32 cpu_mask(void);
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#endif /* _FSL_LAYERSCAPE_CPU_H */
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