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https://github.com/smaeul/u-boot.git
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137 lines
3.4 KiB
C
137 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include "comphy_core.h"
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#include "comphy_hpipe.h"
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/*
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* comphy_mux_check_config()
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* description: this function passes over the COMPHY lanes and check if the type
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* is valid for specific lane. If the type is not valid,
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* the function update the struct and set the type of the lane as
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* PHY_TYPE_UNCONNECTED
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*/
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static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
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struct comphy_map *comphy_map_data, int comphy_max_lanes)
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{
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struct comphy_mux_options *mux_opt;
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int lane, opt, valid;
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debug_enter();
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for (lane = 0; lane < comphy_max_lanes;
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lane++, comphy_map_data++, mux_data++) {
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/* Don't check ignored COMPHYs */
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if (comphy_map_data->type == PHY_TYPE_IGNORE)
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continue;
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mux_opt = mux_data->mux_values;
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for (opt = 0, valid = 0; opt < mux_data->max_lane_values;
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opt++, mux_opt++) {
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if (mux_opt->type == comphy_map_data->type) {
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valid = 1;
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break;
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}
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}
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if (valid == 0) {
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debug("lane number %d, had invalid type %d\n",
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lane, comphy_map_data->type);
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debug("set lane %d as type %d\n", lane,
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PHY_TYPE_UNCONNECTED);
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comphy_map_data->type = PHY_TYPE_UNCONNECTED;
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} else {
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debug("lane number %d, has type %d\n",
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lane, comphy_map_data->type);
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}
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}
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debug_exit();
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}
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static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data,
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u32 type, int lane)
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{
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struct comphy_mux_options *mux_opt;
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int opt;
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u32 value = 0;
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debug_enter();
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mux_opt = mux_data->mux_values;
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for (opt = 0 ; opt < mux_data->max_lane_values; opt++, mux_opt++) {
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if (mux_opt->type == type) {
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value = mux_opt->mux_value;
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break;
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}
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}
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debug_exit();
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return value;
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}
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static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
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struct comphy_map *comphy_map_data,
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int comphy_max_lanes,
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void __iomem *selector_base,
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const fdt32_t *mux_lane_order, u32 bitcount)
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{
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u32 lane, value, offset, mask;
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debug_enter();
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for (lane = 0; lane < comphy_max_lanes;
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lane++, comphy_map_data++, mux_data++) {
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if (comphy_map_data->type == PHY_TYPE_IGNORE)
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continue;
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/*
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* if the order of nodes in selector base register is
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* nontrivial, use mapping from mux_lane_order
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*/
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if (mux_lane_order)
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offset = fdt32_to_cpu(mux_lane_order[lane]) * bitcount;
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else
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offset = lane * bitcount;
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mask = (((1 << bitcount) - 1) << offset);
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value = (comphy_mux_get_mux_value(mux_data,
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comphy_map_data->type,
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lane) << offset);
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reg_set(selector_base, value, mask);
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}
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debug_exit();
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}
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void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg,
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struct comphy_map *comphy_map_data,
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void __iomem *selector_base)
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{
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struct comphy_mux_data *mux_data;
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const fdt32_t *mux_lane_order;
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u32 mux_bitcount;
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u32 comphy_max_lanes;
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debug_enter();
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comphy_max_lanes = chip_cfg->comphy_lanes_count;
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mux_data = chip_cfg->mux_data;
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mux_lane_order = chip_cfg->comphy_mux_lane_order;
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mux_bitcount = chip_cfg->comphy_mux_bitcount;
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/* check if the configuration is valid */
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comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes);
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/* Init COMPHY selectors */
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comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes,
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selector_base, mux_lane_order, mux_bitcount);
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debug_exit();
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}
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