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https://github.com/smaeul/u-boot.git
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af6ba90048
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2 platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
67 lines
1.3 KiB
C
67 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#include <dm.h>
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#include <errno.h>
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#include <wdt.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CORE0_POKE_OFFSET 0x50000
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#define CORE0_POKE_OFFSET_MASK 0xfffffULL
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struct octeontx_wdt {
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void __iomem *reg;
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};
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static int octeontx_wdt_reset(struct udevice *dev)
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{
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struct octeontx_wdt *priv = dev_get_priv(dev);
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writeq(~0ULL, priv->reg);
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return 0;
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}
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static int octeontx_wdt_probe(struct udevice *dev)
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{
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struct octeontx_wdt *priv = dev_get_priv(dev);
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priv->reg = dev_remap_addr(dev);
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if (!priv->reg)
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return -EINVAL;
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/*
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* Save core poke register address in reg (its not 0xa0000 as
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* extracted from the DT but 0x50000 instead)
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*/
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priv->reg = (void __iomem *)(((u64)priv->reg &
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~CORE0_POKE_OFFSET_MASK) |
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CORE0_POKE_OFFSET);
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return 0;
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}
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static const struct wdt_ops octeontx_wdt_ops = {
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.reset = octeontx_wdt_reset,
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};
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static const struct udevice_id octeontx_wdt_ids[] = {
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{ .compatible = "arm,sbsa-gwdt" },
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{}
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};
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U_BOOT_DRIVER(wdt_octeontx) = {
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.name = "wdt_octeontx",
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.id = UCLASS_WDT,
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.of_match = octeontx_wdt_ids,
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.ops = &octeontx_wdt_ops,
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.priv_auto_alloc_size = sizeof(struct octeontx_wdt),
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.probe = octeontx_wdt_probe,
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};
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