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2fccd2d96b
This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* Copyright (c) 2011, Google Inc. All rights reserved.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_GPIO_H_
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#define _TEGRA_GPIO_H_
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#define TEGRA_GPIOS_PER_PORT 8
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#define TEGRA_PORTS_PER_BANK 4
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#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
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#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_PORT(x) (((x) >> 3) & 0x3)
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#define GPIO_FULLPORT(x) ((x) >> 3)
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#define GPIO_BIT(x) ((x) & 0x7)
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enum tegra_gpio_init {
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TEGRA_GPIO_INIT_IN,
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TEGRA_GPIO_INIT_OUT0,
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TEGRA_GPIO_INIT_OUT1,
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};
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struct tegra_gpio_config {
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u32 gpio:16;
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u32 init:2;
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};
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/**
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* tegra_spl_gpio_direction_output() - set the output value of a GPIO
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*
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* This function is only used from SPL on seaboard, which needs to enable a
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* GPIO to get the UART running. It could be done in U-Boot rather than SPL,
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* but for now, this gets it working
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*/
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int tegra_spl_gpio_direction_output(int gpio, int value);
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/**
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* Configure a list of GPIOs
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*
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* @param config List of GPIO configurations
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* @param len Number of config items in list
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*/
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void gpio_config_table(const struct tegra_gpio_config *config, int len);
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#endif /* TEGRA_GPIO_H_ */
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