Rick Chen dda00ae4ef riscv: ax25: Andes specific cache shall only support in M-mode ...

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

2019-04-08 09:45:08 +08:00

..

ax25

riscv: ax25: Andes specific cache shall only support in M-mode

2019-04-08 09:45:08 +08:00

generic

riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems

2019-02-27 09:12:33 +08:00

cpu.c

riscv: add support for multi-hart systems

2019-04-08 09:44:26 +08:00

Makefile

riscv: Move trap handler codes to mtrap.S

2018-12-18 09:56:27 +08:00

mtrap.S

riscv: Return to previous privilege level after trap handling

2018-12-18 09:56:27 +08:00

start.S

riscv: hang if relocation of secondary harts fails

2019-04-08 09:44:26 +08:00

u-boot.lds

riscv: Make start.S available for all targets

2018-10-03 17:48:14 +08:00