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https://github.com/smaeul/u-boot.git
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
79 lines
1.5 KiB
C
79 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (c) 2015 Paul Thacker <paul.thacker@microchip.com>
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*
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*/
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#ifndef __PIC32_REGS_H__
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#define __PIC32_REGS_H__
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#include <asm/io.h>
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/* System Configuration */
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#define PIC32_CFG_BASE 0x1f800000
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/* System config register offsets */
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#define CFGCON 0x0000
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#define DEVID 0x0020
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#define SYSKEY 0x0030
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#define PMD1 0x0040
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#define PMD7 0x00a0
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#define CFGEBIA 0x00c0
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#define CFGEBIC 0x00d0
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#define CFGPG 0x00e0
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#define CFGMPLL 0x0100
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/* Non Volatile Memory (NOR flash) */
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#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
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/* Oscillator Configuration */
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#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
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/* Peripheral Pin Select Input */
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#define PPS_IN_BASE 0x1f801400
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/* Peripheral Pin Select Output */
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#define PPS_OUT_BASE 0x1f801500
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/* Pin Config */
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#define PINCTRL_BASE 0x1f860000
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/* USB Core */
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#define PIC32_USB_CORE_BASE 0x1f8e3000
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#define PIC32_USB_CTRL_BASE 0x1f884000
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/* SPI1-SPI6 */
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#define PIC32_SPI1_BASE 0x1f821000
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/* Prefetch Module */
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#define PREFETCH_BASE 0x1f8e0000
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/* DDR2 Controller */
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#define PIC32_DDR2C_BASE 0x1f8e8000
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/* DDR2 PHY */
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#define PIC32_DDR2P_BASE 0x1f8e9100
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/* EBI */
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#define PIC32_EBI_BASE 0x1f8e1000
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/* SQI */
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#define PIC32_SQI_BASE 0x1f8e2000
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struct pic32_reg_atomic {
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u32 raw;
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u32 clr;
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u32 set;
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u32 inv;
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};
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#define _CLR_OFFSET 0x04
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#define _SET_OFFSET 0x08
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#define _INV_OFFSET 0x0c
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static inline void __iomem *pic32_get_syscfg_base(void)
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{
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return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
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}
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/* Core */
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const char *get_core_name(void);
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#endif /* __PIC32_REGS_H__ */
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