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fc8c76f42e
Replace the barrier functions in arch/riscv/include/asm/io.h with those defined in barrier.h, which is imported from Linux. This version is modified to remove the include statement of asm-generic/barrier.h, which is not available in U-Boot or required. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
68 lines
1.9 KiB
C
68 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2013 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* Taken from Linux arch/riscv/include/asm/barrier.h, which is based on
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* arch/arm/include/asm/barrier.h
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*/
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#ifndef _ASM_RISCV_BARRIER_H
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#define _ASM_RISCV_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() __asm__ __volatile__ ("nop")
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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/* These barriers need to enforce ordering on both devices or memory. */
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#define mb() RISCV_FENCE(iorw,iorw)
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#define rmb() RISCV_FENCE(ir,ir)
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#define wmb() RISCV_FENCE(ow,ow)
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/* These barriers do not need to enforce ordering on devices, just memory. */
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#define __smp_mb() RISCV_FENCE(rw,rw)
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#define __smp_rmb() RISCV_FENCE(r,r)
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#define __smp_wmb() RISCV_FENCE(w,w)
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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RISCV_FENCE(rw,w); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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RISCV_FENCE(r,rw); \
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___p1; \
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})
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/*
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* This is a very specific barrier: it's currently only used in two places in
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* the kernel, both in the scheduler. See include/linux/spinlock.h for the two
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* orderings it guarantees, but the "critical section is RCsc" guarantee
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* mandates a barrier on RISC-V. The sequence looks like:
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*
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* lr.aq lock
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* sc lock <= LOCKED
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* smp_mb__after_spinlock()
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* // critical section
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* lr lock
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* sc.rl lock <= UNLOCKED
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*
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* The AQ/RL pair provides a RCpc critical section, but there's not really any
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* way we can take advantage of that here because the ordering is only enforced
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* on that one lock. Thus, we're just doing a full fence.
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*/
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#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_BARRIER_H */
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