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Add documention for the x86 'mtrr' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
152 lines
5.8 KiB
ReStructuredText
152 lines
5.8 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+:
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mtrr command
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============
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Synopis
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-------
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mtrr [list]
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mtrr set <reg> <type> <start> <size>
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mtrr disable <reg>
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mtrr enable
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Description
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-----------
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The *mtrr* command is used to dump the Memory Type Range Registers (MTRRs) on
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an x86 machine. These register control cache behaviour in selected memory
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ranges.
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Note that the number of registers can vary between CPUs.
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mtrr [list]
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~~~~~~~~~~~
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List the MTRRs. The table shows the following information:
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Reg
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Register number (the first is register 0)
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Valid
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Shows Y if the register is valid (has bit 11 set), N if not
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Write-type
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Shows the behaviour when writing to the memory region. The types are
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abbreviated to fit a reasonable line length. Valid types shown below.
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====== ============== ====================================================
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Value Type Meaning
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====== ============== ====================================================
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0 Uncacheable Skip cache and write directly to memory
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1 Combine Multiple writes can be combined into one transaction
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4 Through Update cache and also write to memory
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5 Protect Writes are prohibited
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6 Back Update cache but don't write to memory
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====== ============== ====================================================
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Base
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Base memory address from which the register controls behaviour
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Mask
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Mask value, which also indicates the size
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Size
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Length of memory region within which the register controls behaviour
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mtrr set
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~~~~~~~~
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This sets the value of a particular MTRR. Parameters are:
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reg
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Register number to set, with 0 being the first
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type
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Access type to set. See Write-type above for valid types. This uses the name
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rather than its numeric value.
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start
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Base memory address from which the register should control behaviour
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size
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Length of memory region within which the register controls behaviour
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mtrr disable
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~~~~~~~~~~~~
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This disables a particular register, by clearing its `valid` bit (11).
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mtrr enable
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~~~~~~~~~~~
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This enables a particular register, by setting its `valid` bit (11).
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Example
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-------
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This shows disabling and enabling an MTRR, as well as setting its type::
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=> mtrr
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CPU 0:
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Reg Valid Write-type Base || Mask || Size ||
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0 Y Back 0000000000000000 0000000f80000000 0000000080000000
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1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
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2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
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3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
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4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
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5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000
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6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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=> mtrr d 5
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=> mtrr
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CPU 0:
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Reg Valid Write-type Base || Mask || Size ||
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0 Y Back 0000000000000000 0000000f80000000 0000000080000000
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1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
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2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
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3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
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4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
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5 N Combine 00000000d0000000 0000000ff0000000 0000000010000000
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6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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=> mtrr e 5
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=> mtrr
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CPU 0:
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Reg Valid Write-type Base || Mask || Size ||
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0 Y Back 0000000000000000 0000000f80000000 0000000080000000
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1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
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2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
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3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
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4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
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5 Y Combine 00000000d0000000 0000000ff0000000 0000000010000000
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6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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=> mtrr set 5 Uncacheable d0000000 10000000
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=> mtrr
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CPU 0:
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Reg Valid Write-type Base || Mask || Size ||
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0 Y Back 0000000000000000 0000000f80000000 0000000080000000
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1 Y Back 0000000080000000 0000000fe0000000 0000000020000000
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2 Y Back 00000000a0000000 0000000ff0000000 0000000010000000
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3 Y Uncacheable 00000000ad000000 0000000fff000000 0000000001000000
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4 Y Uncacheable 00000000ae000000 0000000ffe000000 0000000002000000
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5 Y Uncacheable 00000000d0000000 0000000ff0000000 0000000010000000
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6 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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7 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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8 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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9 N Uncacheable 0000000000000000 0000000000000000 0000001000000000
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=>
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