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				https://github.com/smaeul/u-boot.git
				synced 2025-11-03 21:48:15 +00:00 
			
		
		
		
	This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
		
			
				
	
	
		
			59 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			59 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (c) 2016 Google, Inc
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 *
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 * SPDX-License-Identifier:	GPL-2.0
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 */
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#ifndef __asm_arch_rcba_h
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#define __asm_arch_rcba_h
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#define PMSYNC_CONFIG	0x33c4	/* 32bit */
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#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
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#define DEEP_S3_POL	0x3328	/* 32bit */
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#define  DEEP_S3_EN_AC		(1 << 0)
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#define  DEEP_S3_EN_DC		(1 << 1)
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#define DEEP_S5_POL	0x3330	/* 32bit */
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#define  DEEP_S5_EN_AC		(1 << 14)
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#define  DEEP_S5_EN_DC		(1 << 15)
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#define DEEP_SX_CONFIG	0x3334	/* 32bit */
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#define  DEEP_SX_WAKE_PIN_EN	(1 << 2)
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#define  DEEP_SX_ACPRESENT_PD	(1 << 1)
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#define  DEEP_SX_GP27_PIN_EN	(1 << 0)
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#define PMSYNC_CONFIG	0x33c4	/* 32bit */
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#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
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#define RC		0x3400	/* 32bit */
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#define HPTC		0x3404	/* 32bit */
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#define GCS		0x3410	/* 32bit */
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#define BUC		0x3414	/* 32bit */
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#define PCH_DISABLE_GBE		(1 << 5)
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#define FD		0x3418	/* 32bit */
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#define FDSW		0x3420	/* 8bit */
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#define DISPBDF		0x3424  /* 16bit */
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#define FD2		0x3428	/* 32bit */
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#define CG		0x341c	/* 32bit */
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/* Function Disable 1 RCBA 0x3418 */
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#define PCH_DISABLE_ALWAYS	(1 << 0)
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#define PCH_DISABLE_ADSPD	(1 << 1)
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#define PCH_DISABLE_SATA1	(1 << 2)
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#define PCH_DISABLE_SMBUS	(1 << 3)
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#define PCH_DISABLE_HD_AUDIO	(1 << 4)
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#define PCH_DISABLE_EHCI2	(1 << 13)
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#define PCH_DISABLE_LPC		(1 << 14)
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#define PCH_DISABLE_EHCI1	(1 << 15)
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#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
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#define PCH_DISABLE_THERMAL	(1 << 24)
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#define PCH_DISABLE_SATA2	(1 << 25)
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#define PCH_DISABLE_XHCI	(1 << 27)
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/* Function Disable 2 RCBA 0x3428 */
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#define PCH_DISABLE_KT		(1 << 4)
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#define PCH_DISABLE_IDER	(1 << 3)
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#define PCH_DISABLE_MEI2	(1 << 2)
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#define PCH_DISABLE_MEI1	(1 << 1)
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#define PCH_ENABLE_DBDF		(1 << 0)
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#endif
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