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c196110777
Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
198 lines
5.5 KiB
C
198 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_CLK_MT8512_H
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#define _DT_BINDINGS_CLK_MT8512_H
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/* TOPCKGEN */
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#define CLK_TOP_CLK_NULL 0
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#define CLK_TOP_CLK32K 1
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#define CLK_TOP_SYSPLL1_D2 2
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#define CLK_TOP_SYSPLL1_D4 3
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#define CLK_TOP_SYSPLL1_D8 4
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#define CLK_TOP_SYSPLL1_D16 5
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#define CLK_TOP_SYSPLL_D3 6
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#define CLK_TOP_SYSPLL2_D2 7
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#define CLK_TOP_SYSPLL2_D4 8
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#define CLK_TOP_SYSPLL2_D8 9
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#define CLK_TOP_SYSPLL_D5 10
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#define CLK_TOP_SYSPLL3_D4 11
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#define CLK_TOP_SYSPLL_D7 12
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#define CLK_TOP_SYSPLL4_D2 13
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#define CLK_TOP_UNIVPLL 14
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#define CLK_TOP_UNIVPLL_D2 15
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#define CLK_TOP_UNIVPLL1_D2 16
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#define CLK_TOP_UNIVPLL1_D4 17
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#define CLK_TOP_UNIVPLL1_D8 18
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#define CLK_TOP_UNIVPLL_D3 19
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#define CLK_TOP_UNIVPLL2_D2 20
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#define CLK_TOP_UNIVPLL2_D4 21
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#define CLK_TOP_UNIVPLL2_D8 22
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#define CLK_TOP_UNIVPLL_D5 23
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#define CLK_TOP_UNIVPLL3_D2 24
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#define CLK_TOP_UNIVPLL3_D4 25
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#define CLK_TOP_TCONPLL_D2 26
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#define CLK_TOP_TCONPLL_D4 27
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#define CLK_TOP_TCONPLL_D8 28
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#define CLK_TOP_TCONPLL_D16 29
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#define CLK_TOP_TCONPLL_D32 30
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#define CLK_TOP_TCONPLL_D64 31
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#define CLK_TOP_USB20_192M 32
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#define CLK_TOP_USB20_192M_D2 33
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#define CLK_TOP_USB20_192M_D4_T 34
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#define CLK_TOP_APLL1 35
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#define CLK_TOP_APLL1_D2 36
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#define CLK_TOP_APLL1_D3 37
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#define CLK_TOP_APLL1_D4 38
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#define CLK_TOP_APLL1_D8 39
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#define CLK_TOP_APLL1_D16 40
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#define CLK_TOP_APLL2 41
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#define CLK_TOP_APLL2_D2 42
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#define CLK_TOP_APLL2_D3 43
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#define CLK_TOP_APLL2_D4 44
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#define CLK_TOP_APLL2_D8 45
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#define CLK_TOP_APLL2_D16 46
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#define CLK_TOP_CLK26M 47
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#define CLK_TOP_SYS_26M_D2 48
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#define CLK_TOP_MSDCPLL 49
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#define CLK_TOP_MSDCPLL_D2 50
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#define CLK_TOP_DSPPLL 51
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#define CLK_TOP_DSPPLL_D2 52
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#define CLK_TOP_DSPPLL_D4 53
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#define CLK_TOP_DSPPLL_D8 54
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#define CLK_TOP_IPPLL 55
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#define CLK_TOP_IPPLL_D2 56
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#define CLK_TOP_NFI2X_CK_D2 57
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#define CLK_TOP_AXI_SEL 58
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#define CLK_TOP_MEM_SEL 59
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#define CLK_TOP_UART_SEL 60
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#define CLK_TOP_SPI_SEL 61
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#define CLK_TOP_SPIS_SEL 62
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#define CLK_TOP_MSDC50_0_HC_SEL 63
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#define CLK_TOP_MSDC2_2_HC_SEL 64
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#define CLK_TOP_MSDC50_0_SEL 65
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#define CLK_TOP_MSDC50_2_SEL 66
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#define CLK_TOP_MSDC30_1_SEL 67
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#define CLK_TOP_AUDIO_SEL 68
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#define CLK_TOP_AUD_INTBUS_SEL 69
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#define CLK_TOP_HAPLL1_SEL 70
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#define CLK_TOP_HAPLL2_SEL 71
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#define CLK_TOP_A2SYS_SEL 72
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#define CLK_TOP_A1SYS_SEL 73
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#define CLK_TOP_ASM_L_SEL 74
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#define CLK_TOP_ASM_M_SEL 75
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#define CLK_TOP_ASM_H_SEL 76
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#define CLK_TOP_AUD_SPDIF_SEL 77
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#define CLK_TOP_AUD_1_SEL 78
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#define CLK_TOP_AUD_2_SEL 79
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#define CLK_TOP_SSUSB_SYS_SEL 80
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#define CLK_TOP_SSUSB_XHCI_SEL 81
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#define CLK_TOP_SPM_SEL 82
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#define CLK_TOP_I2C_SEL 83
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#define CLK_TOP_PWM_SEL 84
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#define CLK_TOP_DSP_SEL 85
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#define CLK_TOP_NFI2X_SEL 86
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#define CLK_TOP_SPINFI_SEL 87
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#define CLK_TOP_ECC_SEL 88
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#define CLK_TOP_GCPU_SEL 89
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#define CLK_TOP_GCPU_CPM_SEL 90
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#define CLK_TOP_MBIST_DIAG_SEL 91
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#define CLK_TOP_IP0_NNA_SEL 92
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#define CLK_TOP_IP1_NNA_SEL 93
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#define CLK_TOP_IP2_WFST_SEL 94
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#define CLK_TOP_SFLASH_SEL 95
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#define CLK_TOP_SRAM_SEL 96
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#define CLK_TOP_MM_SEL 97
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#define CLK_TOP_DPI0_SEL 98
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#define CLK_TOP_DBG_ATCLK_SEL 99
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#define CLK_TOP_OCC_104M_SEL 100
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#define CLK_TOP_OCC_68M_SEL 101
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#define CLK_TOP_OCC_182M_SEL 102
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/* TOPCKGEN Gates */
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#define CLK_TOP_CONN_32K 0
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#define CLK_TOP_CONN_26M 1
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#define CLK_TOP_DSP_32K 2
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#define CLK_TOP_DSP_26M 3
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#define CLK_TOP_USB20_48M_EN 4
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#define CLK_TOP_UNIVPLL_48M_EN 5
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#define CLK_TOP_SSUSB_TOP_CK_EN 6
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#define CLK_TOP_SSUSB_PHY_CK_EN 7
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#define CLK_TOP_I2SI1_MCK 8
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#define CLK_TOP_TDMIN_MCK 9
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#define CLK_TOP_I2SO1_MCK 10
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/* INFRASYS */
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#define CLK_INFRA_DSP_AXI 0
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#define CLK_INFRA_APXGPT 1
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#define CLK_INFRA_ICUSB 2
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#define CLK_INFRA_GCE 3
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#define CLK_INFRA_THERM 4
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#define CLK_INFRA_PWM_HCLK 5
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#define CLK_INFRA_PWM1 6
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#define CLK_INFRA_PWM2 7
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#define CLK_INFRA_PWM3 8
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#define CLK_INFRA_PWM4 9
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#define CLK_INFRA_PWM5 10
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#define CLK_INFRA_PWM 11
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#define CLK_INFRA_UART0 12
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#define CLK_INFRA_UART1 13
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#define CLK_INFRA_UART2 14
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#define CLK_INFRA_DSP_UART 15
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#define CLK_INFRA_GCE_26M 16
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#define CLK_INFRA_CQDMA_FPC 17
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#define CLK_INFRA_BTIF 18
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#define CLK_INFRA_SPI 19
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#define CLK_INFRA_MSDC0 20
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#define CLK_INFRA_MSDC1 21
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#define CLK_INFRA_DVFSRC 22
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#define CLK_INFRA_GCPU 23
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#define CLK_INFRA_TRNG 24
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#define CLK_INFRA_AUXADC 25
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#define CLK_INFRA_AUXADC_MD 26
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#define CLK_INFRA_AP_DMA 27
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#define CLK_INFRA_DEBUGSYS 28
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#define CLK_INFRA_AUDIO 29
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#define CLK_INFRA_FLASHIF 30
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#define CLK_INFRA_PWM_FB6 31
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#define CLK_INFRA_PWM_FB7 32
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#define CLK_INFRA_AUD_ASRC 33
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#define CLK_INFRA_AUD_26M 34
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#define CLK_INFRA_SPIS 35
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#define CLK_INFRA_CQ_DMA 36
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#define CLK_INFRA_AP_MSDC0 37
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#define CLK_INFRA_MD_MSDC0 38
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#define CLK_INFRA_MSDC0_SRC 39
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#define CLK_INFRA_MSDC1_SRC 40
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#define CLK_INFRA_IRRX_26M 41
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#define CLK_INFRA_IRRX_32K 42
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#define CLK_INFRA_I2C0_AXI 43
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#define CLK_INFRA_I2C1_AXI 44
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#define CLK_INFRA_I2C2_AXI 45
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#define CLK_INFRA_NFI 46
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#define CLK_INFRA_NFIECC 47
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#define CLK_INFRA_NFI_HCLK 48
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#define CLK_INFRA_SUSB_133 49
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#define CLK_INFRA_USB_SYS 50
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#define CLK_INFRA_USB_XHCI 51
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#define CLK_INFRA_NR_CLK 52
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL2 2
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#define CLK_APMIXED_MSDCPLL 3
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#define CLK_APMIXED_APLL1 4
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#define CLK_APMIXED_APLL2 5
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#define CLK_APMIXED_IPPLL 6
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#define CLK_APMIXED_DSPPLL 7
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#define CLK_APMIXED_TCONPLL 8
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#define CLK_APMIXED_NR_CLK 9
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#endif /* _DT_BINDINGS_CLK_MT8512_H */
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