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161 lines
4.4 KiB
C
161 lines
4.4 KiB
C
/*
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* Power and Sleep Controller (PSC) functions.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2004 Texas Instruments.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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/*
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* The PSC manages three inputs to a "module" which may be a peripheral or
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* CPU. Those inputs are the module's: clock; reset signal; and sometimes
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* its power domain. For our purposes, we only care whether clock and power
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* are active, and the module is out of reset.
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*
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* DaVinci chips may include two separate power domains: "Always On" and "DSP".
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* Chips without a DSP generally have only one domain.
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*
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* The "Always On" power domain is always on when the chip is on, and is
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* powered by the VDD pins (on DM644X). The majority of DaVinci modules
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* lie within the "Always On" power domain.
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*
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* A separate domain called the "DSP" domain houses the C64x+ and other video
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* hardware such as VICP. In some chips, the "DSP" domain is not always on.
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* The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
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*/
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/* Works on Always On power domain only (no PD argument) */
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void lpsc_on(unsigned int id)
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{
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dv_reg_p mdstat, mdctl, ptstat, ptcmd;
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#ifdef CONFIG_SOC_DA8XX
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struct davinci_psc_regs *psc_regs;
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#endif
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#ifndef CONFIG_SOC_DA8XX
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if (id >= DAVINCI_LPSC_GEM)
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return; /* Don't work on DSP Power Domain */
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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ptstat = REG_P(PSC_PTSTAT);
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ptcmd = REG_P(PSC_PTCMD);
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#else
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if (id < DAVINCI_LPSC_PSC1_BASE) {
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if (id >= PSC_PSC0_MODULE_ID_CNT)
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return;
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psc_regs = davinci_psc0_regs;
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mdstat = &psc_regs->psc0.mdstat[id];
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mdctl = &psc_regs->psc0.mdctl[id];
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} else {
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id -= DAVINCI_LPSC_PSC1_BASE;
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if (id >= PSC_PSC1_MODULE_ID_CNT)
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return;
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psc_regs = davinci_psc1_regs;
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mdstat = &psc_regs->psc1.mdstat[id];
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mdctl = &psc_regs->psc1.mdctl[id];
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}
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ptstat = &psc_regs->ptstat;
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ptcmd = &psc_regs->ptcmd;
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#endif
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while (readl(ptstat) & 0x01)
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continue;
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if ((readl(mdstat) & 0x1f) == 0x03)
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return; /* Already on and enabled */
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writel(readl(mdctl) | 0x03, mdctl);
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switch (id) {
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#ifdef CONFIG_SOC_DM644X
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/* Special treatment for some modules as for sprue14 p.7.4.2 */
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case DAVINCI_LPSC_VPSSSLV:
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case DAVINCI_LPSC_EMAC:
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case DAVINCI_LPSC_EMAC_WRAPPER:
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case DAVINCI_LPSC_MDIO:
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case DAVINCI_LPSC_USB:
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case DAVINCI_LPSC_ATA:
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case DAVINCI_LPSC_VLYNQ:
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case DAVINCI_LPSC_UHPI:
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case DAVINCI_LPSC_DDR_EMIF:
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case DAVINCI_LPSC_AEMIF:
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case DAVINCI_LPSC_MMC_SD:
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case DAVINCI_LPSC_MEMSTICK:
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case DAVINCI_LPSC_McBSP:
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case DAVINCI_LPSC_GPIO:
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writel(readl(mdctl) | 0x200, mdctl);
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break;
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#endif
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}
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writel(0x01, ptcmd);
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while (readl(ptstat) & 0x01)
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continue;
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while ((readl(mdstat) & 0x1f) != 0x03)
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continue;
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}
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/* Not all DaVinci chips have a DSP power domain. */
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#ifdef CONFIG_SOC_DM644X
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/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
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#if !defined(CONFIG_SYS_USE_DSPLINK)
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void dsp_on(void)
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{
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int i;
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if (REG(PSC_PDSTAT1) & 0x1f)
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return; /* Already on */
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REG(PSC_GBLCTL) |= 0x01;
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REG(PSC_PDCTL1) |= 0x01;
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REG(PSC_PDCTL1) &= ~0x100;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
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REG(PSC_PTCMD) = 0x02;
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for (i = 0; i < 100; i++) {
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if (REG(PSC_EPCPR) & 0x02)
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break;
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}
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REG(PSC_CHP_SHRTSW) = 0x01;
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REG(PSC_PDCTL1) |= 0x100;
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REG(PSC_EPCCR) = 0x02;
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for (i = 0; i < 100; i++) {
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if (!(REG(PSC_PTSTAT) & 0x02))
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break;
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}
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REG(PSC_GBLCTL) &= ~0x1f;
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}
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#endif /* CONFIG_SYS_USE_DSPLINK */
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#endif /* have a DSP */
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