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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
168 lines
3.6 KiB
ArmAsm
168 lines
3.6 KiB
ArmAsm
/*
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* Copyright 2004, 2007, 2008 Freescale Semiconductor.
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* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <mpc86xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/* If this is a multi-cpu system then we need to handle the
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* 2nd cpu. The assumption is that the 2nd cpu is being
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* held in boot holdoff mode until the 1st cpu unlocks it
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* from Linux. We'll do some basic cpu init and then pass
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* it to the Linux Reset Vector.
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* Sri: Much of this initialization is not required. Linux
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* rewrites the bats, and the sprs and also enables the L1 cache.
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*
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* Core 0 must copy this to a 1M aligned region and set BPTR
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* to point to it.
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*/
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.align 12
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.globl __secondary_start_page
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__secondary_start_page:
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.space 0x100 /* space over to reset vector loc */
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mfspr r0, MSSCR0
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andi. r0, r0, 0x0020
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rlwinm r0,r0,27,31,31
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mtspr PIR, r0
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/* Invalidate BATs */
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li r0, 0
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mtspr IBAT0U, r0
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mtspr IBAT1U, r0
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mtspr IBAT2U, r0
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mtspr IBAT3U, r0
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mtspr IBAT4U, r0
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mtspr IBAT5U, r0
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mtspr IBAT6U, r0
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mtspr IBAT7U, r0
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isync
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mtspr DBAT0U, r0
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mtspr DBAT1U, r0
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mtspr DBAT2U, r0
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mtspr DBAT3U, r0
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mtspr DBAT4U, r0
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mtspr DBAT5U, r0
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mtspr DBAT6U, r0
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mtspr DBAT7U, r0
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isync
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sync
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/* enable extended addressing */
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mfspr r0, HID0
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lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
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ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
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mtspr HID0, r0
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sync
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isync
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#ifdef CONFIG_SYS_L2
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/* init the L2 cache */
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addis r3, r0, L2_INIT@h
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ori r3, r3, L2_INIT@l
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sync
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mtspr l2cr, r3
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#ifdef CONFIG_ALTIVEC
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dssall
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#endif
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/* invalidate the L2 cache */
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mfspr r3, l2cr
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rlwinm. r3, r3, 0, 0, 0
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beq 1f
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mfspr r3, l2cr
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rlwinm r3, r3, 0, 1, 31
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#ifdef CONFIG_ALTIVEC
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dssall
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#endif
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sync
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mtspr l2cr, r3
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sync
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1: mfspr r3, l2cr
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oris r3, r3, L2CR_L2I@h
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mtspr l2cr, r3
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invl2:
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mfspr r3, l2cr
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andis. r3, r3, L2CR_L2I@h
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bne invl2
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sync
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#endif
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/* enable and invalidate the data cache */
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mfspr r3, HID0
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li r5, HID0_DCFI|HID0_DLOCK
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andc r3, r3, r5
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mtspr HID0, r3 /* no invalidate, unlock */
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ori r3, r3, HID0_DCE
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ori r5, r3, HID0_DCFI
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mtspr HID0, r5 /* enable + invalidate */
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mtspr HID0, r3 /* enable */
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sync
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#ifdef CONFIG_SYS_L2
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sync
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lis r3, L2_ENABLE@h
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ori r3, r3, L2_ENABLE@l
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mtspr l2cr, r3
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isync
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sync
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#endif
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/* enable and invalidate the instruction cache*/
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mfspr r3, HID0
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li r5, HID0_ICFI|HID0_ILOCK
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andc r3, r3, r5
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ori r3, r3, HID0_ICE
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ori r5, r3, HID0_ICFI
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mtspr HID0, r5
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mtspr HID0, r3
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isync
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sync
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/* TBEN in HID0 */
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mfspr r4, HID0
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oris r4, r4, 0x0400
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mtspr HID0, r4
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sync
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isync
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/* MCP|SYNCBE|ABE in HID1 */
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mfspr r4, HID1
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oris r4, r4, 0x8000
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ori r4, r4, 0x0C00
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mtspr HID1, r4
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sync
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isync
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lis r3, CONFIG_LINUX_RESET_VEC@h
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ori r3, r3, CONFIG_LINUX_RESET_VEC@l
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mtlr r3
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blr
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/* Never Returns, Running in Linux Now */
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