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cf87d3b503
Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
// SPDX-License-Identifier: Intel
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/*
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* Mostly taken from coreboot fsp2_0/silicon_init.c
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*/
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#define LOG_CATEGORY UCLASS_NORTHBRIDGE
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#include <common.h>
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#include <binman.h>
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#include <dm.h>
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#include <asm/arch/fsp/fsp_configs.h>
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#include <asm/arch/fsp/fsp_s_upd.h>
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#include <asm/fsp/fsp_infoheader.h>
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#include <asm/fsp2/fsp_internal.h>
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int fsp_silicon_init(bool s3wake, bool use_spi_flash)
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{
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struct fsps_upd upd, *fsp_upd;
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fsp_silicon_init_func func;
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struct fsp_header *hdr;
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struct binman_entry entry;
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struct udevice *dev;
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ulong rom_offset = 0;
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int ret;
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ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr,
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&rom_offset);
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if (ret)
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return log_msg_ret("locate FSP", ret);
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gd->arch.fsp_s_hdr = hdr;
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/* Copy over the default config */
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fsp_upd = (struct fsps_upd *)(hdr->img_base + hdr->cfg_region_off);
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if (fsp_upd->header.signature != FSPS_UPD_SIGNATURE)
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return log_msg_ret("Bad UPD signature", -EPERM);
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memcpy(&upd, fsp_upd, sizeof(upd));
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ret = fsps_update_config(dev, rom_offset, &upd);
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if (ret)
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return log_msg_ret("Could not setup config", ret);
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log_debug("Silicon init...");
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bootstage_start(BOOTSTATE_ID_ACCUM_FSP_S, "fsp-s");
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func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
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ret = func(&upd);
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bootstage_accum(BOOTSTATE_ID_ACCUM_FSP_S);
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if (ret)
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return log_msg_ret("Silicon init fail\n", ret);
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log_debug("done\n");
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return 0;
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}
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