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121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _VIRTEX2_H_
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#define _VIRTEX2_H_
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#include <xilinx.h>
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extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size );
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extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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extern int Virtex2_info( Xilinx_desc *desc );
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extern int Virtex2_reloc( Xilinx_desc *desc, ulong reloc_off );
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/*
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* Slave SelectMap Implementation function table.
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*/
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_init_fn init;
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Xilinx_err_fn err;
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Xilinx_done_fn done;
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Xilinx_clk_fn clk;
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Xilinx_cs_fn cs;
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Xilinx_wr_fn wr;
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Xilinx_rdata_fn rdata;
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Xilinx_wdata_fn wdata;
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Xilinx_busy_fn busy;
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Xilinx_abort_fn abort;
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Xilinx_post_fn post;
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int relocated;
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} Xilinx_Virtex2_Slave_SelectMap_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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Xilinx_pgm_fn pgm;
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Xilinx_clk_fn clk;
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Xilinx_rdata_fn rdata;
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Xilinx_wdata_fn wdata;
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int relocated;
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} Xilinx_Virtex2_Slave_Serial_fns;
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/* Device Image Sizes (in bytes)
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*********************************************************************/
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#define XILINX_XC2V40_SIZE (338208 / 8)
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#define XILINX_XC2V80_SIZE (597408 / 8)
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#define XILINX_XC2V250_SIZE (1591584 / 8)
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#define XILINX_XC2V500_SIZE (2557857 / 8)
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#define XILINX_XC2V1000_SIZE (3749408 / 8)
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#define XILINX_XC2V1500_SIZE (5166240 / 8)
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#define XILINX_XC2V2000_SIZE (6808352 / 8)
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#define XILINX_XC2V3000_SIZE (9589408 / 8)
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#define XILINX_XC2V4000_SIZE (14220192 / 8)
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#define XILINX_XC2V6000_SIZE (19752096 / 8)
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#define XILINX_XC2V8000_SIZE (26185120 / 8)
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#define XILINX_XC2V10000_SIZE (33519264 / 8)
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/* Descriptor Macros
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*********************************************************************/
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#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
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#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
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#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
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#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
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#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
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#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
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#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
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#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
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#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
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#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
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#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
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#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
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#endif /* _VIRTEX2_H_ */
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/* vim: set ts=4 tw=78: */
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