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2bf7c86ebb
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/*
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* UniPhier SC (System Control) block registers for ARMv8 SoCs
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*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef SC64_REGS_H
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#define SC64_REGS_H
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#define SC_BASE_ADDR 0x61840000
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#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
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#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
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#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
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#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
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#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
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#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
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#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
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#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
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#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
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#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
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#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
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#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
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#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
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#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
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#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
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#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
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#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
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#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
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#define SC_CA_GEARUPD (1 << 0)
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#endif /* SC64_REGS_H */
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