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https://github.com/smaeul/u-boot.git
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fc3dab4fbe
configuration should be done before release host wait Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Host interface (LPC or eSPI) configuration on Nuvoton BMC
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitfield.h>
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#define SMC_CTL_REG_ADDR 0xc0001001
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#define SMC_CTL_HOSTWAIT 0x80
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/* GCR Register Offsets */
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#define HIFCR 0x50
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#define MFSEL1 0x260
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#define MFSEL4 0x26c
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/* ESPI Register offsets */
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#define ESPICFG 0x4
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#define ESPIHINDP 0x80
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/* MFSEL bit fileds */
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#define MFSEL1_LPCSEL BIT(26)
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#define MFSEL4_ESPISEL BIT(8)
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/* ESPICFG bit fileds */
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#define CHSUPP_MASK GENMASK(27, 24)
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#define IOMODE_MASK GENMASK(9, 8)
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#define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3)
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#define MAXFREQ_MASK GENMASK(12, 10)
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#define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2)
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/* ESPIHINDP bit fileds */
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#define AUTO_SBLD BIT(4)
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#define AUTO_HS1 BIT(8)
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#define AUTO_HS2 BIT(12)
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#define AUTO_HS3 BIT(16)
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static int npcm_host_intf_bind(struct udevice *dev)
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{
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struct regmap *syscon;
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void __iomem *base;
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u32 ch_supp, val;
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u32 ioaddr;
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const char *type;
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int ret;
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syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
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if (IS_ERR(syscon)) {
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dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name);
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return PTR_ERR(syscon);
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}
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ioaddr = dev_read_u32_default(dev, "ioaddr", 0);
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if (ioaddr)
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regmap_write(syscon, HIFCR, ioaddr);
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type = dev_read_string(dev, "type");
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if (!type)
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return -EINVAL;
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if (!strcmp(type, "espi")) {
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base = dev_read_addr_ptr(dev);
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if (!base)
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return -EINVAL;
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ret = dev_read_u32(dev, "channel-support", &ch_supp);
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if (ret)
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return ret;
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/* Select eSPI pins function */
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regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0);
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regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL);
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val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp;
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writel(val, base + ESPIHINDP);
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val = readl(base + ESPICFG);
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val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK);
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val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp);
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writel(val, base + ESPICFG);
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} else if (!strcmp(type, "lpc")) {
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/* Select LPC pin function */
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regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0);
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regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL);
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}
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/* Release host wait */
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setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
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return 0;
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}
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static const struct udevice_id npcm_hostintf_ids[] = {
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{ .compatible = "nuvoton,npcm750-host-intf" },
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{ .compatible = "nuvoton,npcm845-host-intf" },
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{ }
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};
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U_BOOT_DRIVER(npcm_host_intf) = {
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.name = "npcm_host_intf",
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.id = UCLASS_MISC,
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.of_match = npcm_hostintf_ids,
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.bind = npcm_host_intf_bind,
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};
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