mirror of
https://github.com/smaeul/u-boot.git
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0008e9a69d
Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
125 lines
3.2 KiB
C
125 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <config.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <pci.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <misc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <asm/arch/csrs/csrs-xcv.h>
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#define XCVX_BASE 0x87E0DB000000ULL
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/* Initialize XCV block */
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void xcv_init_hw(void)
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{
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union xcvx_reset reset;
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union xcvx_dll_ctl xcv_dll_ctl;
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/* Take the DLL out of reset */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.dllrst = 0;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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/* Take the clock tree out of reset */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.clkrst = 0;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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/* Once the 125MHz ref clock is stable, wait 10us for DLL to lock */
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udelay(10);
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/* Optionally, bypass the DLL setting */
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xcv_dll_ctl.u = readq(XCVX_BASE + XCVX_DLL_CTL(0));
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xcv_dll_ctl.s.clkrx_set = 0;
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xcv_dll_ctl.s.clkrx_byp = 1;
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xcv_dll_ctl.s.clktx_byp = 0;
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writeq(xcv_dll_ctl.u, XCVX_BASE + XCVX_DLL_CTL(0));
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/* Enable the compensation controller */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.comp = 1;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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/* Wait for 1040 reference clock cycles for the compensation state
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* machine lock.
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*/
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udelay(100);
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/* Enable the XCV block */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.enable = 1;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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/* set XCV(0)_RESET[CLKRST] to 1 */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.clkrst = 1;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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}
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/*
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* Configure XCV link based on the speed
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* link_up : Set to 1 when link is up otherwise 0
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* link_speed: The speed of the link.
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*/
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void xcv_setup_link(bool link_up, int link_speed)
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{
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union xcvx_ctl xcv_ctl;
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union xcvx_reset reset;
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union xcvx_batch_crd_ret xcv_crd_ret;
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int speed = 2;
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/* Check RGMII link */
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if (link_speed == 100)
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speed = 1;
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else if (link_speed == 10)
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speed = 0;
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if (link_up) {
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/* Set operating speed */
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xcv_ctl.u = readq(XCVX_BASE + XCVX_CTL(0));
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xcv_ctl.s.speed = speed;
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writeq(xcv_ctl.u, XCVX_BASE + XCVX_CTL(0));
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/* Datapaths come out of reset
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* - The datapath resets will disengage BGX from the
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* RGMII interface
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* - XCV will continue to return TX credits for each tick
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* that is sent on the TX data path
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*/
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.tx_dat_rst_n = 1;
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reset.s.rx_dat_rst_n = 1;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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/* Enable packet flow */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.tx_pkt_rst_n = 1;
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reset.s.rx_pkt_rst_n = 1;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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xcv_crd_ret.u = readq(XCVX_BASE + XCVX_BATCH_CRD_RET(0));
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xcv_crd_ret.s.crd_ret = 1;
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writeq(xcv_crd_ret.u, XCVX_BASE + XCVX_BATCH_CRD_RET(0));
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} else {
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/* Enable packet flow */
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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reset.s.tx_pkt_rst_n = 0;
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reset.s.rx_pkt_rst_n = 0;
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writeq(reset.u, XCVX_BASE + XCVX_RESET(0));
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reset.u = readq(XCVX_BASE + XCVX_RESET(0));
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}
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}
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