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e8b4a8d7f0
The adin phy has extended registers that can be accessed using
adin_ext_read and adin_ext_write. These registers can be read directly
using the mdio command using readext and writext. For example:
=> mdio rx ethernet@428a0000 0xff23
Reading from bus ethernet@428a0000
PHY at address 0:
65315 - 0xe01
Signed-off-by: Nate Drude <nate.d@variscite.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
278 lines
7.4 KiB
C
278 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/**
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* Driver for Analog Devices Industrial Ethernet PHYs
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*
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* Copyright 2019 Analog Devices Inc.
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* Copyright 2022 Variscite Ltd.
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* Copyright 2022 Josua Mayer <josua@solid-run.com>
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*/
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#include <common.h>
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#include <phy.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#define PHY_ID_ADIN1300 0x0283bc30
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#define ADIN1300_EXT_REG_PTR 0x10
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#define ADIN1300_EXT_REG_DATA 0x11
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#define ADIN1300_GE_CLK_CFG_REG 0xff1f
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#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)
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#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5)
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#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4)
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#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3)
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#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2)
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#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1)
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#define ADIN1300_GE_CLK_CFG_25 BIT(0)
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#define ADIN1300_GE_RGMII_CFG 0xff23
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#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
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#define ADIN1300_GE_RGMII_RX_SEL(x) \
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FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
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#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
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#define ADIN1300_GE_RGMII_GTX_SEL(x) \
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FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
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#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
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#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
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#define ADIN1300_GE_RGMII_EN BIT(0)
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/* RGMII internal delay settings for rx and tx for ADIN1300 */
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#define ADIN1300_RGMII_1_60_NS 0x0001
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#define ADIN1300_RGMII_1_80_NS 0x0002
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#define ADIN1300_RGMII_2_00_NS 0x0000
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#define ADIN1300_RGMII_2_20_NS 0x0006
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#define ADIN1300_RGMII_2_40_NS 0x0007
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/**
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* struct adin_cfg_reg_map - map a config value to aregister value
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* @cfg value in device configuration
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* @reg value in the register
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*/
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struct adin_cfg_reg_map {
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int cfg;
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int reg;
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};
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static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
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{ 1600, ADIN1300_RGMII_1_60_NS },
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{ 1800, ADIN1300_RGMII_1_80_NS },
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{ 2000, ADIN1300_RGMII_2_00_NS },
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{ 2200, ADIN1300_RGMII_2_20_NS },
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{ 2400, ADIN1300_RGMII_2_40_NS },
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{ },
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};
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static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
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{
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size_t i;
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for (i = 0; tbl[i].cfg; i++) {
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if (tbl[i].cfg == cfg)
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return tbl[i].reg;
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}
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return -EINVAL;
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}
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static u32 adin_get_reg_value(struct phy_device *phydev,
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const char *prop_name,
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const struct adin_cfg_reg_map *tbl,
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u32 dflt)
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{
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u32 val;
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int rc;
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ofnode node = phy_get_ofnode(phydev);
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if (!ofnode_valid(node)) {
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printf("%s: failed to get node\n", __func__);
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return -EINVAL;
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}
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if (ofnode_read_u32(node, prop_name, &val)) {
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printf("%s: failed to find %s, using default %d\n",
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__func__, prop_name, dflt);
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return dflt;
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}
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debug("%s: %s = '%d'\n", __func__, prop_name, val);
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rc = adin_lookup_reg_value(tbl, val);
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if (rc < 0) {
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printf("%s: Unsupported value %u for %s using default (%u)\n",
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__func__, val, prop_name, dflt);
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return dflt;
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}
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return rc;
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}
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/**
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* adin_get_phy_mode_override - Get phy-mode override for adin PHY
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*
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* The function gets phy-mode string from property 'adi,phy-mode-override'
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* and return its index in phy_interface_strings table, or -1 in error case.
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*/
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phy_interface_t adin_get_phy_mode_override(struct phy_device *phydev)
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{
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ofnode node = phy_get_ofnode(phydev);
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const char *phy_mode_override;
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const char *prop_phy_mode_override = "adi,phy-mode-override";
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int i;
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phy_mode_override = ofnode_read_string(node, prop_phy_mode_override);
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if (!phy_mode_override)
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return PHY_INTERFACE_MODE_NA;
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debug("%s: %s = '%s'\n",
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__func__, prop_phy_mode_override, phy_mode_override);
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for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++)
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if (!strcmp(phy_mode_override, phy_interface_strings[i]))
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return (phy_interface_t) i;
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printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode_override);
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return PHY_INTERFACE_MODE_NA;
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}
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static u16 adin_ext_read(struct phy_device *phydev, const u32 regnum)
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{
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u16 val;
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phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_PTR, regnum);
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val = phy_read(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA);
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debug("%s: adin@0x%x 0x%x=0x%x\n", __func__, phydev->addr, regnum, val);
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return val;
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}
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static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16 val)
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{
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debug("%s: adin@0x%x 0x%x=0x%x\n", __func__, phydev->addr, regnum, val);
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phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_PTR, regnum);
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return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val);
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}
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static int adin_extread(struct phy_device *phydev, int addr, int devaddr,
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int regnum)
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{
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return adin_ext_read(phydev, regnum);
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}
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static int adin_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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return adin_ext_write(phydev, regnum, val);
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}
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static int adin_config_clk_out(struct phy_device *phydev)
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{
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ofnode node = phy_get_ofnode(phydev);
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const char *val = NULL;
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u8 sel = 0;
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val = ofnode_read_string(node, "adi,phy-output-clock");
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if (!val) {
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/* property not present, do not enable GP_CLK pin */
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} else if (strcmp(val, "25mhz-reference") == 0) {
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sel |= ADIN1300_GE_CLK_CFG_25;
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} else if (strcmp(val, "125mhz-free-running") == 0) {
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sel |= ADIN1300_GE_CLK_CFG_FREE_125;
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} else if (strcmp(val, "adaptive-free-running") == 0) {
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sel |= ADIN1300_GE_CLK_CFG_HRT_FREE;
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} else {
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pr_err("%s: invalid adi,phy-output-clock\n", __func__);
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return -EINVAL;
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}
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if (ofnode_read_bool(node, "adi,phy-output-reference-clock"))
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sel |= ADIN1300_GE_CLK_CFG_REF_EN;
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return adin_ext_write(phydev, ADIN1300_GE_CLK_CFG_REG,
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ADIN1300_GE_CLK_CFG_MASK & sel);
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}
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static int adin_config_rgmii_mode(struct phy_device *phydev)
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{
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u16 reg_val;
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u32 val;
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phy_interface_t phy_mode_override = adin_get_phy_mode_override(phydev);
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if (phy_mode_override != PHY_INTERFACE_MODE_NA) {
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phydev->interface = phy_mode_override;
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}
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reg_val = adin_ext_read(phydev, ADIN1300_GE_RGMII_CFG);
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if (!phy_interface_is_rgmii(phydev)) {
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/* Disable RGMII */
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reg_val &= ~ADIN1300_GE_RGMII_EN;
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return adin_ext_write(phydev, ADIN1300_GE_RGMII_CFG, reg_val);
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}
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/* Enable RGMII */
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reg_val |= ADIN1300_GE_RGMII_EN;
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/* Enable / Disable RGMII RX Delay */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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reg_val |= ADIN1300_GE_RGMII_RXID_EN;
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val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
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adin_rgmii_delays,
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ADIN1300_RGMII_2_00_NS);
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reg_val &= ~ADIN1300_GE_RGMII_RX_MSK;
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reg_val |= ADIN1300_GE_RGMII_RX_SEL(val);
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} else {
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reg_val &= ~ADIN1300_GE_RGMII_RXID_EN;
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}
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/* Enable / Disable RGMII RX Delay */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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reg_val |= ADIN1300_GE_RGMII_TXID_EN;
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val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
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adin_rgmii_delays,
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ADIN1300_RGMII_2_00_NS);
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reg_val &= ~ADIN1300_GE_RGMII_GTX_MSK;
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reg_val |= ADIN1300_GE_RGMII_GTX_SEL(val);
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} else {
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reg_val &= ~ADIN1300_GE_RGMII_TXID_EN;
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}
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return adin_ext_write(phydev, ADIN1300_GE_RGMII_CFG, reg_val);
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}
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static int adin1300_config(struct phy_device *phydev)
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{
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int ret;
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printf("ADIN1300 PHY detected at addr %d\n", phydev->addr);
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ret = adin_config_clk_out(phydev);
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if (ret < 0)
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return ret;
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ret = adin_config_rgmii_mode(phydev);
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if (ret < 0)
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return ret;
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return genphy_config(phydev);
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}
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U_BOOT_PHY_DRIVER(ADIN1300) = {
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.name = "ADIN1300",
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.uid = PHY_ID_ADIN1300,
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.mask = 0xffffffff,
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.features = PHY_GBIT_FEATURES,
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.config = adin1300_config,
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.startup = genphy_startup,
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.shutdown = genphy_shutdown,
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.readext = adin_extread,
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.writeext = adin_extwrite,
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};
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