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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
204 lines
6.1 KiB
C
204 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Multirate Ethernet MAC(MRMAC) driver
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*
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* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
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* Michal Simek <michal.simek@amd.com>
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*
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* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
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*/
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#ifndef __XILINX_AXI_MRMAC_H
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#define __XILINX_AXI_MRMAC_H
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#define MIN_PKT_SIZE 60
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/* MRMAC needs atleast two buffer descriptors for Tx/Rx to work.
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* Otherwise MRMAC will drop the packets. So, have atleast two Tx and
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* two Rx bd's.
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*/
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#define TX_DESC 2
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#define RX_DESC 2
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/* MRMAC platform data structure */
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struct axi_mrmac_plat {
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struct eth_pdata eth_pdata;
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struct mcdma_common_regs *mm2s_cmn;
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u32 mrmac_rate; /* Hold the value from DT property "mrmac-rate" */
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};
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/* MRMAC private driver structure */
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struct axi_mrmac_priv {
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struct mrmac_regs *iobase;
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struct mcdma_common_regs *mm2s_cmn;
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struct mcdma_common_regs *s2mm_cmn;
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struct mcdma_chan_reg *mcdma_tx;
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struct mcdma_chan_reg *mcdma_rx;
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struct mcdma_bd *tx_bd[TX_DESC];
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struct mcdma_bd *rx_bd[RX_DESC];
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u8 *txminframe; /* Pointer to hold min length Tx frame(60) */
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u32 mrmac_rate; /* Speed to configure(Read from DT 10G/25G..) */
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};
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/* MRMAC Register Definitions */
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struct mrmac_regs {
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u32 revision; /* 0x0: Revision Register */
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u32 reset; /* 0x4: Reset Register */
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u32 mode; /* 0x8: Mode */
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u32 tx_config; /* 0xc: Tx Configuration */
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u32 rx_config; /* 0x10: Rx Configuration */
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u32 reserved[6];/* 0x14-0x28: Reserved */
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u32 tick_reg; /* 0x2c: Tick Register */
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};
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#define TX_BD_TOTAL_SIZE (TX_DESC * sizeof(struct mcdma_bd))
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#define RX_BD_TOTAL_SIZE (RX_DESC * sizeof(struct mcdma_bd))
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#define RX_BUFF_TOTAL_SIZE (RX_DESC * PKTSIZE_ALIGN)
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/* Status Registers */
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#define MRMAC_TX_STS_OFFSET 0x740
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#define MRMAC_RX_STS_OFFSET 0x744
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#define MRMAC_TX_RT_STS_OFFSET 0x748
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#define MRMAC_RX_RT_STS_OFFSET 0x74c
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#define MRMAC_STATRX_BLKLCK_OFFSET 0x754
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/* Register bit masks */
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#define MRMAC_RX_SERDES_RST_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0))
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#define MRMAC_TX_SERDES_RST_MASK BIT(4)
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#define MRMAC_RX_RST_MASK BIT(5)
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#define MRMAC_TX_RST_MASK BIT(6)
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#define MRMAC_RX_AXI_RST_MASK BIT(8)
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#define MRMAC_TX_AXI_RST_MASK BIT(9)
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#define MRMAC_STS_ALL_MASK 0xffffffff
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#define MRMAC_RX_EN_MASK BIT(0)
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#define MRMAC_RX_DEL_FCS_MASK BIT(1)
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#define MRMAC_TX_EN_MASK BIT(0)
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#define MRMAC_TX_INS_FCS_MASK BIT(1)
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#define MRMAC_RX_BLKLCK_MASK BIT(0)
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#define MRMAC_TICK_TRIGGER BIT(0)
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#define MRMAC_RESET_DELAY 1 /* Delay in msecs */
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#define MRMAC_BLKLCK_TIMEOUT 100 /* Block lock timeout in msecs */
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#define MRMAC_DMARST_TIMEOUT 500 /* MCDMA reset timeout in msecs */
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#define XMCDMA_RX_OFFSET 0x500
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#define XMCDMA_CHAN_OFFSET 0x40
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/* MCDMA Channel numbers are from 1-16 */
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#define XMCDMA_CHANNEL_1 BIT(0)
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#define XMCDMA_CHANNEL_2 BIT(1)
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#define XMCDMA_CR_RUNSTOP BIT(0)
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#define XMCDMA_CR_RESET BIT(2)
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#define XMCDMA_BD_CTRL_TXSOF_MASK BIT(31) /* First tx packet */
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#define XMCDMA_BD_CTRL_TXEOF_MASK BIT(30) /* Last tx packet */
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#define XMCDMA_BD_CTRL_ALL_MASK GENMASK(31, 30) /* All control bits */
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#define XMCDMA_BD_STS_ALL_MASK GENMASK(31, 28) /* All status bits */
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/* MCDMA Mask registers */
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#define XMCDMA_CR_RUNSTOP_MASK BIT(0) /* Start/stop DMA channel */
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#define XMCDMA_CR_RESET_MASK BIT(2) /* Reset DMA engine */
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#define XMCDMA_SR_HALTED_MASK BIT(0)
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#define XMCDMA_SR_IDLE_MASK BIT(1)
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#define XMCDMA_CH_IDLE BIT(0)
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#define XMCDMA_BD_STS_COMPLETE BIT(31) /* Completed */
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#define XMCDMA_BD_STS_DEC_ERR BIT(20) /* Decode error */
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#define XMCDMA_BD_STS_SLV_ERR BIT(29) /* Slave error */
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#define XMCDMA_BD_STS_INT_ERR BIT(28) /* Internal err */
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#define XMCDMA_BD_STS_ALL_ERR GENMASK(30, 28) /* All errors */
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#define XMCDMA_IRQ_ERRON_OTHERQ_MASK BIT(3)
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#define XMCDMA_IRQ_PKTDROP_MASK BIT(4)
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#define XMCDMA_IRQ_IOC_MASK BIT(5)
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#define XMCDMA_IRQ_DELAY_MASK BIT(6)
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#define XMCDMA_IRQ_ERR_MASK BIT(7)
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#define XMCDMA_IRQ_ALL_MASK GENMASK(7, 5)
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#define XMCDMA_PKTDROP_COALESCE_MASK GENMASK(15, 8)
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#define XMCDMA_COALESCE_MASK GENMASK(23, 16)
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#define XMCDMA_DELAY_MASK GENMASK(31, 24)
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#define MRMAC_CTL_DATA_RATE_MASK GENMASK(2, 0)
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#define MRMAC_CTL_DATA_RATE_10G 0
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#define MRMAC_CTL_DATA_RATE_25G 1
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#define MRMAC_CTL_DATA_RATE_40G 2
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#define MRMAC_CTL_DATA_RATE_50G 3
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#define MRMAC_CTL_DATA_RATE_100G 4
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#define MRMAC_CTL_AXIS_CFG_MASK GENMASK(11, 9)
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#define MRMAC_CTL_AXIS_CFG_SHIFT 9
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#define MRMAC_CTL_AXIS_CFG_10G_IND 1
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#define MRMAC_CTL_AXIS_CFG_25G_IND 1
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#define MRMAC_CTL_SERDES_WIDTH_MASK GENMASK(6, 4)
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#define MRMAC_CTL_SERDES_WIDTH_SHIFT 4
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#define MRMAC_CTL_SERDES_WIDTH_10G 4
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#define MRMAC_CTL_SERDES_WIDTH_25G 6
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#define MRMAC_CTL_RATE_CFG_MASK (MRMAC_CTL_DATA_RATE_MASK | \
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MRMAC_CTL_AXIS_CFG_MASK | \
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MRMAC_CTL_SERDES_WIDTH_MASK)
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#define MRMAC_CTL_PM_TICK_MASK BIT(30)
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#define MRMAC_TICK_TRIGGER BIT(0)
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#define XMCDMA_BD_STS_ACTUAL_LEN_MASK 0x007fffff /* Actual length */
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/* MCDMA common offsets */
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struct mcdma_common_regs {
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u32 control; /* Common control */
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u32 status; /* Common status */
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u32 chen; /* Channel enable/disable */
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u32 chser; /* Channel in progress */
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u32 err; /* Error */
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u32 ch_schd_type; /* Channel Q scheduler type */
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u32 wrr_reg1; /* Weight of each channel (ch1-8) */
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u32 wrr_reg2; /* Weight of each channel (ch9-16) */
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u32 ch_serviced; /* Channels completed */
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u32 arcache_aruser; /* ARCACHE and ARUSER values for AXI4 read */
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u32 intr_status; /* Interrupt monitor */
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u32 reserved[5];
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};
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/* MCDMA per-channel registers */
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struct mcdma_chan_reg {
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u32 control; /* Control */
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u32 status; /* Status */
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u32 current; /* Current descriptor */
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u32 current_hi; /* Current descriptor high 32bit */
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u32 tail; /* Tail descriptor */
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u32 tail_hi; /* Tail descriptor high 32bit */
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u32 pktcnt; /* Packet processed count */
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};
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/* MCDMA buffer descriptors */
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struct mcdma_bd {
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u32 next_desc; /* Next descriptor pointer */
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u32 next_desc_msb;
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u32 buf_addr; /* Buffer address */
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u32 buf_addr_msb;
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u32 reserved1;
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u32 cntrl; /* Control */
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u32 status; /* Status */
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u32 sband_stats;
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u32 app0;
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u32 app1; /* Tx start << 16 | insert */
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u32 app2; /* Tx csum seed */
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u32 app3;
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u32 app4;
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u32 sw_id_offset;
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u32 reserved2;
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u32 reserved3;
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u32 reserved4[16];
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};
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#endif /* __XILINX_AXI_MRMAC_H */
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