mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 20:18:18 +00:00
fcf75435c8
pimg64 image pointer is dependent on ESBC_ADDR_64BIT config, which is getting disabled, due to dependency on ESBC_HDR_LS. ESBC_HDR_LS is required for LS-CH3 platforms. So, removing the dependency on ESBC_HDR_LS. Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
299 lines
7.8 KiB
Plaintext
299 lines
7.8 KiB
Plaintext
menu "Functionality shared between NXP SoCs"
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config FSL_TRUST_ARCH_v1
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bool
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config NXP_ESBC
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bool "NXP ESBC (secure boot) functionality"
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select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
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ARCH_P5040 || ARCH_P2041
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help
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Enable Freescale Secure Boot feature. Normally selected by defconfig.
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If unsure, do not change.
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menu "Chain of trust / secure boot options"
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depends on !FIT_SIGNATURE && NXP_ESBC
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config CHAIN_OF_TRUST
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select FSL_CAAM
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select ARCH_MISC_INIT
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select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
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select FSL_SEC_MON
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select SPL_BOARD_INIT if (ARM && SPL)
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select SPL_HASH if (ARM && SPL)
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select SHA_HW_ACCEL
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select SHA_PROG_HW_ACCEL
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select ENV_IS_NOWHERE
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select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
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select CMD_EXT4 if ARM
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select CMD_EXT4_WRITE if ARM
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imply CMD_BLOB
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imply CMD_HASH if ARM
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def_bool y
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config CMD_ESBC_VALIDATE
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bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
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default y
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help
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This option enables two commands used for secure booting:
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esbc_validate - validate signature using RSA verification
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esbc_halt - put the core in spin loop (Secure Boot Only)
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config ESBC_HDR_LS
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bool
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config ESBC_ADDR_64BIT
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def_bool y
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depends on FSL_LAYERSCAPE
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help
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For Layerscape based platforms, ESBC image Address in Header is 64bit.
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config FSL_ISBC_KEY_EXT
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bool
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help
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The key used for verification of next level images is picked up from
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an Extension Table which has been verified by the ISBC (Internal
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Secure boot Code) in boot ROM of the SoC. The feature is only
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applicable in case of NOR boot and is not applicable in case of
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RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
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for all device if IE Table is copied to XIP memory Also, for
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Layerscape, ISBC doesn't verify this table.
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config SYS_FSL_SFP_BE
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def_bool y
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depends on PPC || FSL_LSCH2 || ARCH_LS1021A
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config SYS_FSL_SFP_LE
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def_bool y
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depends on !SYS_FSL_SFP_BE
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choice
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prompt "SFP IP revision"
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default SYS_FSL_SFP_VER_3_0 if PPC
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default SYS_FSL_SFP_VER_3_4
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config SYS_FSL_SFP_VER_3_0
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bool "SFP version 3.0"
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config SYS_FSL_SFP_VER_3_2
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bool "SFP version 3.2"
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config SYS_FSL_SFP_VER_3_4
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bool "SFP version 3.4"
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endchoice
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config SPL_UBOOT_KEY_HASH
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string "Non-SRK key hash for U-Boot public/private key pair"
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depends on SPL
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default ""
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help
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Set the key hash for U-Boot here if public/private key pair used to
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sign U-Boot are different from the SRK hash put in the fuse. Example
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of a key hash is
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41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
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Otherwise leave this empty.
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if PPC
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config BOOTSCRIPT_COPY_RAM
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bool "Secure boot copies boot script to RAM"
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help
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On systems that support chain of trust booting, a number of addresses
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are required to set variables that are used in the copying and then
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verification of different parts of the system. If enabled, the subsequent
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options are for what location to use in each step.
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config BS_ADDR_DEVICE
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hex "Address in RAM for bs_device"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_SIZE
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hex "The size of bs_size which is the amount read from bs_device"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_ADDR_RAM
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hex "Address in RAM for bs_ram"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_HDR_ADDR_DEVICE
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hex "Address in RAM for bs_hdr_device"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_HDR_SIZE
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hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_HDR_ADDR_RAM
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hex "Address in RAM for bs_hdr_ram"
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depends on BOOTSCRIPT_COPY_RAM
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config BOOTSCRIPT_HDR_ADDR
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hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
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default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
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endif
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config SYS_FSL_SRK_LE
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def_bool y
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depends on ARM
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config KEY_REVOCATION
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def_bool y
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endmenu
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config DEEP_SLEEP
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bool "Enable SoC deep sleep feature"
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depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
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default y
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help
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Indicates this SoC supports deep sleep feature. If deep sleep is
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supported, core will start to execute uboot when wakes up.
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config LAYERSCAPE_NS_ACCESS
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bool "Layerscape non-secure access support"
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depends on ARCH_LS1021A || FSL_LSCH2
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config PCIE1
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bool "PCIe controller #1"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE2
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bool "PCIe controller #2"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE3
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bool "PCIe controller #3"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE4
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bool "PCIe controller #4"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config FSL_USE_PCA9547_MUX
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bool "Enable PCA9547 I2C Mux on Freescale boards"
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depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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help
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This option enables the PCA9547 I2C mux on Freescale boards.
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config VID
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bool "Enable Freescale VID"
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depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
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help
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This option enables setting core voltage based on individual
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values saved in SoC fuses.
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config SPL_VID
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bool "Enable Freescale VID in SPL"
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depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
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help
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This option enables setting core voltage based on individual
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values saved in SoC fuses, in SPL.
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if VID || SPL_VID
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config VID_FLS_ENV
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string "Environment variable for overriding VDD"
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help
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This option allows for specifying the environment variable
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to check to override VDD information.
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config VOL_MONITOR_INA220
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bool "Enable the INA220 voltage monitor read"
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help
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This option enables INA220 voltage monitor read
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_IR36021_READ
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bool "Enable the IR36021 voltage monitor read"
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help
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This option enables IR36021 voltage monitor read
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_IR36021_SET
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bool "Enable the IR36021 voltage monitor set"
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help
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This option enables IR36021 voltage monitor set
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_LTC3882_READ
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bool "Enable the LTC3882 voltage monitor read"
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help
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This option enables LTC3882 voltage monitor read
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_LTC3882_SET
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bool "Enable the LTC3882 voltage monitor set"
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help
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This option enables LTC3882 voltage monitor set
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_ISL68233_READ
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bool "Enable the ISL68233 voltage monitor read"
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help
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This option enables ISL68233 voltage monitor read
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_ISL68233_SET
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bool "Enable the ISL68233 voltage monitor set"
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help
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This option enables ISL68233 voltage monitor set
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functionality. It is used by the common VID driver.
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endif
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config SYS_FSL_NUM_CC_PLLS
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int "Number of clock control PLLs"
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depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
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default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
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default 6 if FSL_LSCH3 || MPC85xx
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config SYS_FSL_ESDHC_BE
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bool
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config SYS_FSL_IFC_BE
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bool
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
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ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
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ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
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ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
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ARCH_BSC9132
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default 3 if ARCH_BSC9131 || ARCH_BSC9132
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default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
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ARCH_B4420 || ARCH_P1010
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default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
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ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
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ARCH_T1024 || ARCH_T2080 || ARCH_C29X
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config FSL_QIXIS
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bool "Enable QIXIS support"
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depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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config QIXIS_I2C_ACCESS
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bool "Access to QIXIS is over i2c"
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depends on FSL_QIXIS
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default y
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config HAS_FSL_DR_USB
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def_bool y
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depends on USB_EHCI_HCD && PPC
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config SYS_DPAA_FMAN
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bool
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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endmenu
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