mirror of
https://github.com/smaeul/u-boot.git
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effe934e50
Add support for the Comvetia i.MX6Q LXR2 board, which is uses the Phytec PFLA02 SoM. Based on the original work from Stefano Babic <sbabic@denx.de>. The Phytec PFLA02 devicetrees are taken from kernel 6.11-rc7. The imx6q-lxr.dts has been submitted upstream: https://lore.kernel.org/linux-devicetree/20240913200906.1753458-3-festevam@gmail.com/ After it gets accepted in mainline (most likely in kernel 6.13), the lxr2 board can then be switched to OF_UPSTREAM and these device trees can be removed from U-Boot. Signed-off-by: Fabio Estevam <festevam@denx.de>
389 lines
9.7 KiB
C
389 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
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// Copyright (C) 2024 Fabio Estevam <festevam@denx.de>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/spi.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <nand.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/sections.h>
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#include <linux/delay.h>
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#include <image.h>
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#include <init.h>
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#include <serial.h>
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#include <spl.h>
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#include <linux/sizes.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static const iomux_v3_cfg_t uart4_pads[] = {
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MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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}
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
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{
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return IMX_GPIO_NR(4, 24);
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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setup_gpmi_nand();
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return 0;
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}
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/*
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* BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
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* see Table 8-11 and Table 5-9
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* BOOT_CFG1[7] = 1 (boot from NAND)
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* BOOT_CFG1[5] = 0 - raw NAND
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* BOOT_CFG1[4] = 0 - default pad settings
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* BOOT_CFG1[3:2] = 00 - devices = 1
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* BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
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* BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
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* BOOT_CFG2[2:1] = 01 - Pages In Block = 64
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* BOOT_CFG2[0] = 0 - Reset time 12ms
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*/
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static const struct boot_mode board_boot_modes[] = {
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/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
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{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
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{"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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{NULL, 0},
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};
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int board_late_init(void)
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{
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add_board_boot_modes(board_boot_modes);
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
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static void phyflex_err006282_workaround(void)
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{
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/*
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* Boards beginning with 1362.2 have the SD4_DAT3 pin connected
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* to the CMIC. If this pin isn't toggled within 10s the boards
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* reset. The pin is unconnected on older boards, so we do not
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* need a check for older boards before applying this fixup.
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*/
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gpio_request(MX6_PHYFLEX_ERR006282, "errata_gpio");
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
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mdelay(2);
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
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mdelay(2);
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gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
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imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT3__GPIO2_IO11);
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gpio_direction_input(MX6_PHYFLEX_ERR006282);
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}
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static const iomux_v3_cfg_t gpios_pads[] = {
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MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_gpios(void)
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{
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imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));
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}
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_sdclk_1 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000030,
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.dram_sdodt0 = 0x00000030,
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.dram_sdodt1 = 0x00000030,
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_sdqs2 = 0x00000028,
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.dram_sdqs3 = 0x00000028,
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.dram_sdqs4 = 0x00000028,
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.dram_sdqs5 = 0x00000028,
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.dram_sdqs6 = 0x00000028,
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.dram_sdqs7 = 0x00000028,
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_dqm2 = 0x00000028,
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.dram_dqm3 = 0x00000028,
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.dram_dqm4 = 0x00000028,
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.dram_dqm5 = 0x00000028,
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.dram_dqm6 = 0x00000028,
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.dram_dqm7 = 0x00000028,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000C0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x30,
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.grp_ctlds = 0x30,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_b2ds = 0x00000028,
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.grp_b3ds = 0x00000028,
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.grp_b4ds = 0x00000028,
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.grp_b5ds = 0x00000028,
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.grp_b6ds = 0x00000028,
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.grp_b7ds = 0x00000028,
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};
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static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00170018,
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.p0_mpwldectrl1 = 0x003B0039,
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.p1_mpwldectrl0 = 0x00350048,
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.p1_mpwldectrl1 = 0x00410052,
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.p0_mpdgctrl0 = 0x03600374,
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.p0_mpdgctrl1 = 0x03680360,
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.p1_mpdgctrl0 = 0x0370037C,
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.p1_mpdgctrl1 = 0x03700350,
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.p0_mprddlctl = 0x3A363234,
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.p1_mprddlctl = 0x3634363C,
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.p0_mpwrdlctl = 0x38383E3C,
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.p1_mpwrdlctl = 0x422A483C,
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};
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/* MT41K64M16JT-125 (1Gb density) */
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 1600,
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.density = 1,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 1,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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.dsize = 2,
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.cs_density = 6,
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.ncs = 2,
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.cs1_mirror = 1,
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.rtt_wr = 1,
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.rtt_nom = 1,
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.walat = 1,
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.ralat = 5,
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.mif3_mode = 3,
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.bi_on = 1,
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.sde_to_rst = 0x10,
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.rst_to_cke = 0x23,
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1,
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.refr = 7,
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};
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC3_BASE_ADDR},
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};
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static const iomux_v3_cfg_t usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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int board_mmc_init(struct bd_info *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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switch (spl_boot_list[0]) {
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case BOOT_DEVICE_SPI:
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spl_boot_list[1] = BOOT_DEVICE_UART;
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break;
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case BOOT_DEVICE_MMC1:
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spl_boot_list[1] = BOOT_DEVICE_SPI;
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spl_boot_list[2] = BOOT_DEVICE_UART;
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break;
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default:
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printf("Boot device %x\n", spl_boot_list[0]);
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}
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}
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static const iomux_v3_cfg_t ecspi3_pads[] = {
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MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
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enable_spi_clk(true, 2);
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}
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void board_init_f(ulong dummy)
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{
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/* setup clock gating */
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* setup AXI */
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gpr_init();
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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setup_spi();
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setup_gpios();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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phyflex_err006282_workaround();
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#endif
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