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5389564b52
Add support for *_lr SOCs. Without this change chips are not going to be properly identified and bitstream programming won't work. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/14d8905a89d1b31fbb2318512cf57eb0256c11be.1722347416.git.michal.simek@amd.com
76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2012-2013, Xilinx, Michal Simek
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*
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* (C) Copyright 2012
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* Joe Hershberger <joe.hershberger@ni.com>
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*/
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#ifndef _ZYNQPL_H_
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#define _ZYNQPL_H_
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#include <xilinx.h>
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#ifdef CONFIG_CMD_ZYNQ_AES
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int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
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u8 bstype);
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#endif
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extern struct xilinx_fpga_op zynq_op;
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#define XILINX_ZYNQ_XC7Z007S 0x3
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#define XILINX_ZYNQ_XC7Z010 0x2
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#define XILINX_ZYNQ_XC7Z010_LR 0x4
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#define XILINX_ZYNQ_XC7Z012S 0x1c
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#define XILINX_ZYNQ_XC7Z014S 0x8
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#define XILINX_ZYNQ_XC7Z015 0x1b
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#define XILINX_ZYNQ_XC7Z020_LR 0x9
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#define XILINX_ZYNQ_XC7Z020 0x7
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#define XILINX_ZYNQ_XC7Z030 0xc
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#define XILINX_ZYNQ_XC7Z035 0x12
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#define XILINX_ZYNQ_XC7Z045 0x11
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#define XILINX_ZYNQ_XC7Z100 0x16
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/* Device Image Sizes */
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#define XILINX_XC7Z007S_SIZE 16669920/8
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#define XILINX_XC7Z010_SIZE 16669920/8
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#define XILINX_XC7Z010_LR_SIZE 16669920/8
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#define XILINX_XC7Z012S_SIZE 28085344/8
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#define XILINX_XC7Z014S_SIZE 32364512/8
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#define XILINX_XC7Z015_SIZE 28085344/8
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#define XILINX_XC7Z020_LR_SIZE 32364512/8
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#define XILINX_XC7Z020_SIZE 32364512/8
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#define XILINX_XC7Z030_SIZE 47839328/8
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#define XILINX_XC7Z035_SIZE 106571232/8
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#define XILINX_XC7Z045_SIZE 106571232/8
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#define XILINX_XC7Z100_SIZE 139330784/8
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/* Device Names */
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#define XILINX_XC7Z007S_NAME "7z007s"
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#define XILINX_XC7Z010_NAME "7z010"
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#define XILINX_XC7Z010_LR_NAME "xc7z010_lr"
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#define XILINX_XC7Z012S_NAME "7z012s"
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#define XILINX_XC7Z014S_NAME "7z014s"
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#define XILINX_XC7Z015_NAME "7z015"
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#define XILINX_XC7Z020_LR_NAME "xa7z020_lr"
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#define XILINX_XC7Z020_NAME "7z020"
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#define XILINX_XC7Z030_NAME "7z030"
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#define XILINX_XC7Z035_NAME "7z035"
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#define XILINX_XC7Z045_NAME "7z045"
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#define XILINX_XC7Z100_NAME "7z100"
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#if defined(CONFIG_FPGA)
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#define ZYNQ_DESC(name) { \
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.idcode = XILINX_ZYNQ_XC##name, \
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.fpga_size = XILINX_XC##name##_SIZE, \
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.devicename = XILINX_XC##name##_NAME \
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}
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#else
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#define ZYNQ_DESC(name) { \
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.idcode = XILINX_ZYNQ_XC##name, \
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.devicename = XILINX_XC##name##_NAME \
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}
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#endif
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#endif /* _ZYNQPL_H_ */
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