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0a668f6d38
This patch adds support for all OcteonTX2 96xx/95xx boards from Marvell. For 96xx boards, use octeontx_96xx_defconfig and for 95xx boards, use octeontx_95xx_defconfig. Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch/board.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define OTX2_MEM_MAP_USED 4
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/* +1 is end of list which needs to be empty */
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#define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
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static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
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{
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.virt = 0x800000000000UL,
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.phys = 0x800000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0x840000000000UL,
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.phys = 0x840000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0x880000000000UL,
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.phys = 0x880000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0x8c0000000000UL,
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.phys = 0x8c0000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}
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};
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struct mm_region *mem_map = otx2_mem_map;
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void mem_map_fill(void)
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{
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int banks = OTX2_MEM_MAP_USED;
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u32 dram_start = CONFIG_SYS_TEXT_BASE;
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for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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otx2_mem_map[banks].virt = dram_start;
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otx2_mem_map[banks].phys = dram_start;
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otx2_mem_map[banks].size = gd->ram_size;
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otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_NON_SHARE;
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banks = banks + 1;
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}
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}
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u64 get_page_table_size(void)
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{
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return 0x80000;
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}
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void reset_cpu(ulong addr)
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{
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}
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