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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
76 lines
1.3 KiB
C
76 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/sections.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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switch (boot_dev_spl) {
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC2;
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case QSPI_BOOT:
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return BOOT_DEVICE_NOR;
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case USB_BOOT:
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return BOOT_DEVICE_BOARD;
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default:
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return BOOT_DEVICE_NONE;
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}
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}
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static void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(2);
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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