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https://github.com/smaeul/u-boot.git
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bdce38965e
When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
121 lines
2.3 KiB
C
121 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Fraunhofer AISEC,
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* Lukas Auer <lukas.auer@aisec.fraunhofer.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/barrier.h>
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#include <asm/smp.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* riscv_send_ipi() - Send inter-processor interrupt (IPI)
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*
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* Platform code must provide this function.
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*
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* @hart: Hart ID of receiving hart
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* @return 0 if OK, -ve on error
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*/
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extern int riscv_send_ipi(int hart);
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/**
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* riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
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*
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* Platform code must provide this function.
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*
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* @hart: Hart ID of hart to be cleared
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* @return 0 if OK, -ve on error
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*/
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extern int riscv_clear_ipi(int hart);
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static int send_ipi_many(struct ipi_data *ipi)
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{
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ofnode node, cpus;
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u32 reg;
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int ret;
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cpus = ofnode_path("/cpus");
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if (!ofnode_valid(cpus)) {
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pr_err("Can't find cpus node!\n");
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return -EINVAL;
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}
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ofnode_for_each_subnode(node, cpus) {
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/* skip if hart is marked as not available in the device tree */
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if (!ofnode_is_available(node))
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continue;
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/* read hart ID of CPU */
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ret = ofnode_read_u32(node, "reg", ®);
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if (ret)
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continue;
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/* skip if it is the hart we are running on */
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if (reg == gd->arch.boot_hart)
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continue;
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if (reg >= CONFIG_NR_CPUS) {
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pr_err("Hart ID %d is out of range, increase CONFIG_NR_CPUS\n",
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reg);
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continue;
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}
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#ifndef CONFIG_XIP
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/* skip if hart is not available */
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if (!(gd->arch.available_harts & (1 << reg)))
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continue;
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#endif
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gd->arch.ipi[reg].addr = ipi->addr;
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gd->arch.ipi[reg].arg0 = ipi->arg0;
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gd->arch.ipi[reg].arg1 = ipi->arg1;
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ret = riscv_send_ipi(reg);
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if (ret) {
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pr_err("Cannot send IPI to hart %d\n", reg);
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return ret;
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}
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}
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return 0;
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}
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void handle_ipi(ulong hart)
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{
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int ret;
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void (*smp_function)(ulong hart, ulong arg0, ulong arg1);
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if (hart >= CONFIG_NR_CPUS)
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return;
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ret = riscv_clear_ipi(hart);
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if (ret) {
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pr_err("Cannot clear IPI of hart %ld\n", hart);
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return;
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}
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__smp_mb();
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smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
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invalidate_icache_all();
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smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
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}
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int smp_call_function(ulong addr, ulong arg0, ulong arg1)
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{
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int ret = 0;
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struct ipi_data ipi;
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ipi.addr = addr;
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ipi.arg0 = arg0;
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ipi.arg1 = arg1;
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ret = send_ipi_many(&ipi);
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return ret;
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}
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