mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
54a08c4139
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
156 lines
3.5 KiB
C
156 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_TRAINING_IP_DB_H_
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#define _DDR3_TRAINING_IP_DB_H_
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enum hws_pattern {
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#if defined(CONFIG_DDR4) /* DDR4 16/32-bit */
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PATTERN_PBS1,/*0*/
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PATTERN_PBS2,
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PATTERN_PBS3,
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PATTERN_TEST,
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PATTERN_RL,
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PATTERN_RL2,
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PATTERN_STATIC_PBS,
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PATTERN_KILLER_DQ0,
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PATTERN_KILLER_DQ1,
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PATTERN_KILLER_DQ2,
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PATTERN_KILLER_DQ3,/*10*/
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PATTERN_KILLER_DQ4,
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PATTERN_KILLER_DQ5,
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PATTERN_KILLER_DQ6,
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PATTERN_KILLER_DQ7,
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PATTERN_KILLER_DQ0_INV,
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PATTERN_KILLER_DQ1_INV,
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PATTERN_KILLER_DQ2_INV,
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PATTERN_KILLER_DQ3_INV,
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PATTERN_KILLER_DQ4_INV,
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PATTERN_KILLER_DQ5_INV,/*20*/
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PATTERN_KILLER_DQ6_INV,
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PATTERN_KILLER_DQ7_INV,
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PATTERN_VREF,
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PATTERN_VREF_INV,
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PATTERN_FULL_SSO0,
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PATTERN_FULL_SSO1,
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PATTERN_FULL_SSO2,
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PATTERN_FULL_SSO3,
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PATTERN_ZERO,
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PATTERN_ONE,
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PATTERN_LAST,
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PATTERN_SSO_FULL_XTALK_DQ0,
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PATTERN_SSO_FULL_XTALK_DQ1,/*30*/
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PATTERN_SSO_FULL_XTALK_DQ2,
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PATTERN_SSO_FULL_XTALK_DQ3,
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PATTERN_SSO_FULL_XTALK_DQ4,
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PATTERN_SSO_FULL_XTALK_DQ5,
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PATTERN_SSO_FULL_XTALK_DQ6,
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PATTERN_SSO_FULL_XTALK_DQ7,
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PATTERN_SSO_XTALK_FREE_DQ0,
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PATTERN_SSO_XTALK_FREE_DQ1,
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PATTERN_SSO_XTALK_FREE_DQ2,
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PATTERN_SSO_XTALK_FREE_DQ3,/*40*/
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PATTERN_SSO_XTALK_FREE_DQ4,
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PATTERN_SSO_XTALK_FREE_DQ5,
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PATTERN_SSO_XTALK_FREE_DQ6,
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PATTERN_SSO_XTALK_FREE_DQ7,
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PATTERN_ISI_XTALK_FREE,
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PATTERN_RESONANCE_1T,
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PATTERN_RESONANCE_2T,
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PATTERN_RESONANCE_3T,
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PATTERN_RESONANCE_4T,
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PATTERN_RESONANCE_5T,/*50*/
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PATTERN_RESONANCE_6T,
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PATTERN_RESONANCE_7T,
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PATTERN_RESONANCE_8T,
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PATTERN_RESONANCE_9T
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#else /* DDR3 16/32-bit */
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PATTERN_PBS1,
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PATTERN_PBS2,
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PATTERN_PBS3,
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PATTERN_TEST,
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PATTERN_RL,
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PATTERN_RL2,
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PATTERN_STATIC_PBS,
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PATTERN_KILLER_DQ0,
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PATTERN_KILLER_DQ1,
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PATTERN_KILLER_DQ2,
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PATTERN_KILLER_DQ3,
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PATTERN_KILLER_DQ4,
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PATTERN_KILLER_DQ5,
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PATTERN_KILLER_DQ6,
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PATTERN_KILLER_DQ7,
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PATTERN_VREF,
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PATTERN_FULL_SSO0,
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PATTERN_FULL_SSO1,
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PATTERN_FULL_SSO2,
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PATTERN_FULL_SSO3,
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PATTERN_LAST,
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PATTERN_SSO_FULL_XTALK_DQ0,
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PATTERN_SSO_FULL_XTALK_DQ1,
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PATTERN_SSO_FULL_XTALK_DQ2,
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PATTERN_SSO_FULL_XTALK_DQ3,
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PATTERN_SSO_FULL_XTALK_DQ4,
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PATTERN_SSO_FULL_XTALK_DQ5,
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PATTERN_SSO_FULL_XTALK_DQ6,
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PATTERN_SSO_FULL_XTALK_DQ7,
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PATTERN_SSO_XTALK_FREE_DQ0,
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PATTERN_SSO_XTALK_FREE_DQ1,
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PATTERN_SSO_XTALK_FREE_DQ2,
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PATTERN_SSO_XTALK_FREE_DQ3,
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PATTERN_SSO_XTALK_FREE_DQ4,
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PATTERN_SSO_XTALK_FREE_DQ5,
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PATTERN_SSO_XTALK_FREE_DQ6,
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PATTERN_SSO_XTALK_FREE_DQ7,
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PATTERN_ISI_XTALK_FREE
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#endif /* CONFIG_64BIT */
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};
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enum mv_wl_supp_mode {
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WRITE_LEVELING_SUPP_REG_MODE,
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WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS,
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WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4,
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WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3,
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WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8
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};
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enum mv_ddr_dev_attribute {
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MV_ATTR_TIP_REV,
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MV_ATTR_PHY_EDGE,
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MV_ATTR_OCTET_PER_INTERFACE,
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MV_ATTR_PLL_BEFORE_INIT,
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MV_ATTR_TUNE_MASK,
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MV_ATTR_INIT_FREQ,
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MV_ATTR_MID_FREQ,
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MV_ATTR_DFS_LOW_FREQ,
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MV_ATTR_DFS_LOW_PHY,
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MV_ATTR_DELAY_ENABLE,
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MV_ATTR_CK_DELAY,
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MV_ATTR_CA_DELAY,
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MV_ATTR_INTERLEAVE_WA,
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MV_ATTR_LAST
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};
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enum mv_ddr_tip_revison {
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MV_TIP_REV_NA,
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MV_TIP_REV_1, /* NP5 */
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MV_TIP_REV_2, /* BC2 */
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MV_TIP_REV_3, /* AC3 */
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MV_TIP_REV_4, /* A-380/A-390 */
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MV_TIP_REV_LAST
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};
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enum mv_ddr_phy_edge {
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MV_DDR_PHY_EDGE_POSITIVE,
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MV_DDR_PHY_EDGE_NEGATIVE
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};
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/* Device attribute functions */
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void ddr3_tip_dev_attr_init(u32 dev_num);
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u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
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void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
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#endif /* _DDR3_TRAINING_IP_DB_H_ */
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