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https://github.com/smaeul/u-boot.git
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400558b561
- rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL - rename memsetup into lowlevel_init (function name and source files)
183 lines
5.3 KiB
ArmAsm
183 lines
5.3 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the TRAB board by
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* (C) Copyright 2002-2003
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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/* some parameters for the board */
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/*
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*
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* Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
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*
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* Copyright (C) 2001 Samsung Electronics by chc, 010406
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*
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* TRAB specific tweaks.
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*
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*/
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/* memory controller */
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#define BWSCON 0x14000000
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/* Bank0 */
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#define B0_Tacs 0x1 /* 1 clk */
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#define B0_Tcos 0x1 /* 1 clk */
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#define B0_Tacc 0x5 /* 8 clk */
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#define B0_Tcoh 0x1 /* 1 clk */
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#define B0_Tah 0x1 /* 1 clk */
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#define B0_Tacp 0x0
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#define B0_PMC 0x0 /* normal */
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/* Bank1 - SRAM */
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#define B1_Tacs 0x1 /* 1 clk */
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#define B1_Tcos 0x1 /* 1 clk */
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#define B1_Tacc 0x5 /* 8 clk */
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#define B1_Tcoh 0x1 /* 1 clk */
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#define B1_Tah 0x1 /* 1 clk */
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#define B1_Tacp 0x0
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#define B1_PMC 0x0 /* normal */
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/* Bank2 - CPLD */
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#define B2_Tacs 0x1 /* 1 clk */
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#define B2_Tcos 0x1 /* 1 clk */
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#define B2_Tacc 0x5 /* 8 clk */
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#define B2_Tcoh 0x1 /* 1 clk */
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#define B2_Tah 0x1 /* 1 clk */
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#define B2_Tacp 0x0
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#define B2_PMC 0x0 /* normal */
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/* Bank3 - setup for the cs8900 */
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#define B3_Tacs 0x3 /* 4 clk */
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#define B3_Tcos 0x3 /* 4 clk */
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#define B3_Tacc 0x7 /* 14 clk */
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#define B3_Tcoh 0x1 /* 1 clk */
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#define B3_Tah 0x0 /* 0 clk */
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#define B3_Tacp 0x3 /* 6 clk */
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#define B3_PMC 0x0 /* normal */
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/* Bank4 */
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#define B4_Tacs 0x0 /* 0 clk */
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#define B4_Tcos 0x0 /* 0 clk */
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#define B4_Tacc 0x7 /* 14 clk */
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#define B4_Tcoh 0x0 /* 0 clk */
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#define B4_Tah 0x0 /* 0 clk */
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#define B4_Tacp 0x0
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#define B4_PMC 0x0 /* normal */
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/* Bank5 */
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#define B5_Tacs 0x0 /* 0 clk */
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#define B5_Tcos 0x0 /* 0 clk */
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#define B5_Tacc 0x7 /* 14 clk */
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#define B5_Tcoh 0x0 /* 0 clk */
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#define B5_Tah 0x0 /* 0 clk */
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#define B5_Tacp 0x0
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#define B5_PMC 0x0 /* normal */
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#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
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/* Bank6 */
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd 0x0 /* 2clk */
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#define B6_SCAN 0x1 /* 9 bit */
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/* Bank7 */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x0 /* 2clk */
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#define B7_SCAN 0x1 /* 9 bit */
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#else /* CONFIG_RAM_16MB = 16 MB RAM */
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/* Bank6 */
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd 0x1 /* 2clk */
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#define B6_SCAN 0x0 /* 8 bit */
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/* Bank7 */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x1 /* 2clk */
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#define B7_SCAN 0x0 /* 8 bit */
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#endif /* CONFIG_RAM_16MB */
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/* refresh parameter */
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#define REFEN 0x1 /* enable refresh */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
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#define Trp 0x0 /* 2 clk */
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#define Trc 0x3 /* 7 clk */
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#define Tchr 0x2 /* 3 clk */
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#ifdef CONFIG_TRAB_50MHZ
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#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
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#else
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#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
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#endif
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_TEXT_BASE:
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.word TEXT_BASE
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.globl lowlevel_init
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lowlevel_init:
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =SMRDATA
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #52
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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SMRDATA:
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.word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
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.word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
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#else /* CONFIG_RAM_16MB = 16 MB RAM */
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.word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
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#endif /* CONFIG_RAM_16MB */
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.word 0x20 /* MRSR6, CL=2clk */
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.word 0x20 /* MRSR7 */
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