mirror of
https://github.com/smaeul/u-boot.git
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343 lines
8.9 KiB
C
343 lines
8.9 KiB
C
/*
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* arch/ppc/kernel/pci_auto.c
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*
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* PCI autoconfiguration library
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DEBUGF(x...) printf(x)
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#else
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#define DEBUGF(x...)
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#endif /* DEBUG */
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#define PCIAUTO_IDE_MODE_MASK 0x05
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/*
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*
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*/
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void pciauto_region_init(struct pci_region* res)
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{
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res->bus_lower = res->bus_start;
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}
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void pciauto_region_align(struct pci_region *res, unsigned long size)
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{
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res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
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}
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int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
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{
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unsigned long addr;
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if (!res) {
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DEBUGF("No resource");
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goto error;
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}
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addr = ((res->bus_lower - 1) | (size - 1)) + 1;
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if (addr - res->bus_start + size > res->size) {
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DEBUGF("No room in resource");
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goto error;
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}
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res->bus_lower = addr + size;
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DEBUGF("address=0x%lx", addr);
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*bar = addr;
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return 0;
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error:
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*bar = 0xffffffff;
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return -1;
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}
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/*
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*
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*/
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void pciauto_setup_device(struct pci_controller *hose,
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pci_dev_t dev, int bars_num,
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struct pci_region *mem,
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struct pci_region *io)
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{
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unsigned int bar_value, bar_response, bar_size;
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unsigned int cmdstat = 0;
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struct pci_region *bar_res;
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int bar, bar_nr = 0;
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int found_mem64 = 0;
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pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
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cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
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for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
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/* Tickle the BAR and get the response */
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pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
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pci_hose_read_config_dword(hose, dev, bar, &bar_response);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_response)
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continue;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
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bar_res = io;
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DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
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} else {
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if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64)
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found_mem64 = 1;
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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bar_res = mem;
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DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
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}
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if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
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/* Write it out and update our limit */
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pci_hose_write_config_dword(hose, dev, bar, bar_value);
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/*
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* If we are a 64-bit decoder then increment to the
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* upper 32 bits of the bar and force it to locate
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* in the lower 4GB of memory.
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*/
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if (found_mem64) {
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bar += 4;
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pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
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}
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cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
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PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
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}
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DEBUGF("\n");
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bar_nr++;
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}
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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}
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static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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{
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struct pci_region *pci_mem = hose->pci_mem;
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struct pci_region *pci_io = hose->pci_io;
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unsigned int cmdstat;
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pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
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/* Configure bus number registers */
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pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
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pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
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pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
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(pci_mem->bus_lower & 0xfff00000) >> 16);
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cmdstat |= PCI_COMMAND_MEMORY;
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
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(pci_io->bus_lower & 0x0000f000) >> 8);
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pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
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(pci_io->bus_lower & 0xffff0000) >> 16);
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cmdstat |= PCI_COMMAND_IO;
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}
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/* We don't support prefetchable memory for now, so disable */
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
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/* Enable memory and I/O accesses, enable bus master */
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
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}
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static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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{
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struct pci_region *pci_mem = hose->pci_mem;
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struct pci_region *pci_io = hose->pci_io;
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/* Configure bus number registers */
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pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
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(pci_mem->bus_lower-1) >> 16);
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
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((pci_io->bus_lower-1) & 0x0000f000) >> 8);
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pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
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((pci_io->bus_lower-1) & 0xffff0000) >> 16);
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}
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}
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/*
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*
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*/
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void pciauto_config_init(struct pci_controller *hose)
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{
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int i;
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hose->pci_io = hose->pci_mem = NULL;
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for (i=0; i<hose->region_count; i++) {
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switch(hose->regions[i].flags) {
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case PCI_REGION_IO:
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if (!hose->pci_io ||
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hose->pci_io->size < hose->regions[i].size)
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hose->pci_io = hose->regions + i;
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break;
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case PCI_REGION_MEM:
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if (!hose->pci_mem ||
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hose->pci_mem->size < hose->regions[i].size)
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hose->pci_mem = hose->regions + i;
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break;
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}
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}
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if (hose->pci_mem) {
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pciauto_region_init(hose->pci_mem);
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DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
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hose->pci_mem->bus_start,
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hose->pci_mem->bus_start + hose->pci_mem->size - 1);
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}
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if (hose->pci_io) {
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pciauto_region_init(hose->pci_io);
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DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
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hose->pci_io->bus_start,
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hose->pci_io->bus_start + hose->pci_io->size - 1);
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}
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}
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/* HJF: Changed this to return int. I think this is required
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* to get the correct result when scanning bridges
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*/
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int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned int sub_bus = PCI_BUS(dev);
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unsigned short class;
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unsigned char prg_iface;
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int n;
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pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
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switch(class) {
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case PCI_CLASS_BRIDGE_PCI:
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hose->current_busno++;
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pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
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DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
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/* Passing in current_busno allows for sibling P2P bridges */
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pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
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/*
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* need to figure out if this is a subordinate bridge on the bus
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* to be able to properly set the pri/sec/sub bridge registers.
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*/
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n = pci_hose_scan_bus(hose, hose->current_busno);
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/* figure out the deepest we've gone for this leg */
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sub_bus = max(n, sub_bus);
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pciauto_postscan_setup_bridge(hose, dev, sub_bus);
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sub_bus = hose->current_busno;
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break;
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case PCI_CLASS_STORAGE_IDE:
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pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
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if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
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DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
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return sub_bus;
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}
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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/* just do a minimal setup of the bridge, let the OS take care of the rest */
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pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
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DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
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hose->current_busno++;
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break;
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#ifdef CONFIG_MPC5200
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case PCI_CLASS_BRIDGE_OTHER:
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DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
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PCI_DEV(dev));
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break;
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#endif
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#ifdef CONFIG_MPC834X
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case PCI_CLASS_BRIDGE_OTHER:
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/*
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* The host/PCI bridge 1 seems broken in 8349 - it presents
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* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
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* device claiming resources io/mem/irq.. we only allow for
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* the PIMMR window to be allocated (BAR0 - 1MB size)
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*/
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DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
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pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
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break;
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#endif
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default:
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
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break;
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}
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return sub_bus;
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}
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#endif /* CONFIG_PCI */
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