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c71645ad2b
This patch add gicv3 support to uboot armv8 platform.
Changes for v2:
- rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
- move smp_kick_all_cpus() from gic.S to start.S, it would be
implementation dependent.
- Each core initialize it's own ReDistributor instead of master
initializeing all ReDistributors. This is advised by arnab.basu
<arnab.basu@freescale.com>.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
111 lines
3.2 KiB
C
111 lines
3.2 KiB
C
#ifndef __GIC_H__
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#define __GIC_H__
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/* Register offsets for the ARM generic interrupt controller (GIC) */
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#define GIC_DIST_OFFSET 0x1000
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#define GIC_CPU_OFFSET_A9 0x0100
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#define GIC_CPU_OFFSET_A15 0x2000
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/* Distributor Registers */
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IIDR 0x0008
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#define GICD_STATUSR 0x0010
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#define GICD_SETSPI_NSR 0x0040
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#define GICD_CLRSPI_NSR 0x0048
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#define GICD_SETSPI_SR 0x0050
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#define GICD_CLRSPI_SR 0x0058
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#define GICD_SEIR 0x0068
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#define GICD_IGROUPRn 0x0080
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#define GICD_ISENABLERn 0x0100
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#define GICD_ICENABLERn 0x0180
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#define GICD_ISPENDRn 0x0200
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#define GICD_ICPENDRn 0x0280
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#define GICD_ISACTIVERn 0x0300
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#define GICD_ICACTIVERn 0x0380
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#define GICD_IPRIORITYRn 0x0400
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#define GICD_ITARGETSRn 0x0800
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#define GICD_ICFGR 0x0c00
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#define GICD_IGROUPMODRn 0x0d00
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#define GICD_NSACRn 0x0e00
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#define GICD_SGIR 0x0f00
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#define GICD_CPENDSGIRn 0x0f10
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#define GICD_SPENDSGIRn 0x0f20
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#define GICD_IROUTERn 0x6000
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/* Cpu Interface Memory Mapped Registers */
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#define GICC_CTLR 0x0000
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#define GICC_PMR 0x0004
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#define GICC_BPR 0x0008
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#define GICC_IAR 0x000C
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#define GICC_EOIR 0x0010
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#define GICC_RPR 0x0014
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#define GICC_HPPIR 0x0018
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#define GICC_ABPR 0x001c
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#define GICC_AIAR 0x0020
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#define GICC_AEOIR 0x0024
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#define GICC_AHPPIR 0x0028
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#define GICC_APRn 0x00d0
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#define GICC_NSAPRn 0x00e0
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#define GICC_IIDR 0x00fc
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#define GICC_DIR 0x1000
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/* ReDistributor Registers for Control and Physical LPIs */
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#define GICR_CTLR 0x0000
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#define GICR_IIDR 0x0004
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR 0x0010
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#define GICR_WAKER 0x0014
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#define GICR_SETLPIR 0x0040
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#define GICR_CLRLPIR 0x0048
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#define GICR_SEIR 0x0068
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#define GICR_PROPBASER 0x0070
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#define GICR_PENDBASER 0x0078
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#define GICR_INVLPIR 0x00a0
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#define GICR_INVALLR 0x00b0
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#define GICR_SYNCR 0x00c0
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#define GICR_MOVLPIR 0x0100
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#define GICR_MOVALLR 0x0110
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/* ReDistributor Registers for SGIs and PPIs */
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#define GICR_IGROUPRn 0x0080
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#define GICR_ISENABLERn 0x0100
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#define GICR_ICENABLERn 0x0180
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#define GICR_ISPENDRn 0x0200
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#define GICR_ICPENDRn 0x0280
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#define GICR_ISACTIVERn 0x0300
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#define GICR_ICACTIVERn 0x0380
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#define GICR_IPRIORITYRn 0x0400
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#define GICR_ICFGR0 0x0c00
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#define GICR_ICFGR1 0x0c04
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#define GICR_IGROUPMODRn 0x0d00
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#define GICR_NSACRn 0x0e00
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/* Cpu Interface System Registers */
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#define ICC_IAR0_EL1 S3_0_C12_C8_0
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#define ICC_IAR1_EL1 S3_0_C12_C12_0
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#define ICC_EOIR0_EL1 S3_0_C12_C8_1
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#define ICC_EOIR1_EL1 S3_0_C12_C12_1
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#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
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#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
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#define ICC_BPR0_EL1 S3_0_C12_C8_3
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#define ICC_BPR1_EL1 S3_0_C12_C12_3
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#define ICC_DIR_EL1 S3_0_C12_C11_1
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_RPR_EL1 S3_0_C12_C11_3
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
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#define ICC_SEIEN_EL1 S3_0_C12_C13_0
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#define ICC_SGI0R_EL1 S3_0_C12_C11_7
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#define ICC_SGI1R_EL1 S3_0_C12_C11_5
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#define ICC_ASGI1R_EL1 S3_0_C12_C11_6
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#endif /* __GIC_H__ */
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