Cem Tenruh 7a478c836a board: phytec: phycore_imx8mm: Update lpddr4_timing ...

Update RAM Timings for 2GB RAM based on DDR Controller Configuration
Spreadsheet revision 22. Including the update of the refresh
rate to workaround errata ERR050805.

Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>

2023-07-13 11:29:40 +02:00

..

pcl063

global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

2022-11-10 10:08:55 -05:00

pcm052

led: Drop led_default_state()

2022-04-28 09:26:44 -04:00

pcm058

global: Use proper project name U-Boot

2023-06-12 13:24:31 +02:00

phycore_am335x_r2

global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG

2022-12-23 10:14:51 -05:00

phycore_imx8mm

board: phytec: phycore_imx8mm: Update lpddr4_timing

2023-07-13 11:29:40 +02:00

phycore_imx8mp

imx: phycore_imx8mm/p: clean up board watchdog code

2022-06-14 21:33:14 +02:00

phycore_rk3288

rockchip: phycore_rk3288: remove phycore_init() function

2022-10-19 19:30:48 +08:00