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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
359 lines
5.5 KiB
ArmAsm
359 lines
5.5 KiB
ArmAsm
/*
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* Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <post.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#if CONFIG_POST & CONFIG_SYS_POST_CPU
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/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
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.global cpu_post_exec_02
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cpu_post_exec_02:
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isync
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mflr r0
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stwu r0, -4(r1)
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subi r1, r1, 104
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stmw r6, 0(r1)
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mtlr r3
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mr r3, r4
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mr r4, r5
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blrl
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lmw r6, 0(r1)
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addi r1, r1, 104
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lwz r0, 0(r1)
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addi r1, r1, 4
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mtlr r0
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blr
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/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
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.global cpu_post_exec_04
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cpu_post_exec_04:
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isync
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mflr r0
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stwu r0, -4(r1)
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subi r1, r1, 96
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stmw r8, 0(r1)
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mtlr r3
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mr r3, r4
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mr r4, r5
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mr r5, r6
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mtxer r7
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blrl
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lmw r8, 0(r1)
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addi r1, r1, 96
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lwz r0, 0(r1)
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addi r1, r1, 4
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mtlr r0
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blr
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/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
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.global cpu_post_exec_12
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cpu_post_exec_12:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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mtlr r3
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mr r3, r5
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mr r4, r6
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blrl
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lwz r4, 0(r1)
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stw r3, 0(r4)
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lwz r0, 4(r1)
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addi r1, r1, 8
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mtlr r0
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blr
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/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
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.global cpu_post_exec_11
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cpu_post_exec_11:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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mtlr r3
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mr r3, r5
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blrl
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lwz r4, 0(r1)
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stw r3, 0(r4)
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lwz r0, 4(r1)
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addi r1, r1, 8
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mtlr r0
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blr
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/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
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.global cpu_post_exec_21
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cpu_post_exec_21:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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stwu r5, -4(r1)
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li r0, 0
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mtxer r0
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lwz r0, 0(r4)
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mtcr r0
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mtlr r3
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mr r3, r6
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blrl
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mfcr r0
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lwz r4, 4(r1)
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stw r0, 0(r4)
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lwz r4, 0(r1)
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stw r3, 0(r4)
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lwz r0, 8(r1)
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addi r1, r1, 12
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mtlr r0
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blr
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/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
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ulong op2); */
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.global cpu_post_exec_22
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cpu_post_exec_22:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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stwu r5, -4(r1)
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li r0, 0
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mtxer r0
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lwz r0, 0(r4)
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mtcr r0
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mtlr r3
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mr r3, r6
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mr r4, r7
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blrl
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mfcr r0
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lwz r4, 4(r1)
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stw r0, 0(r4)
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lwz r4, 0(r1)
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stw r3, 0(r4)
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lwz r0, 8(r1)
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addi r1, r1, 12
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mtlr r0
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blr
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/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
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.global cpu_post_exec_12w
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cpu_post_exec_12w:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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mtlr r3
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lwz r3, 0(r4)
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mr r4, r5
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mr r5, r6
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blrl
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lwz r4, 0(r1)
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stw r3, 0(r4)
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lwz r0, 4(r1)
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addi r1, r1, 8
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mtlr r0
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blr
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/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
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.global cpu_post_exec_11w
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cpu_post_exec_11w:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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mtlr r3
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lwz r3, 0(r4)
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mr r4, r5
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blrl
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lwz r4, 0(r1)
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stw r3, 0(r4)
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lwz r0, 4(r1)
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addi r1, r1, 8
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mtlr r0
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blr
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/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
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.global cpu_post_exec_22w
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cpu_post_exec_22w:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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stwu r6, -4(r1)
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mtlr r3
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lwz r3, 0(r4)
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mr r4, r5
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blrl
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lwz r4, 4(r1)
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stw r3, 0(r4)
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lwz r4, 0(r1)
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stw r5, 0(r4)
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lwz r0, 8(r1)
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addi r1, r1, 12
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mtlr r0
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blr
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/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
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.global cpu_post_exec_21w
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cpu_post_exec_21w:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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stwu r5, -4(r1)
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mtlr r3
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lwz r3, 0(r4)
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blrl
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lwz r5, 4(r1)
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stw r3, 0(r5)
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lwz r5, 0(r1)
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stw r4, 0(r5)
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lwz r0, 8(r1)
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addi r1, r1, 12
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mtlr r0
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blr
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/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
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.global cpu_post_exec_21x
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cpu_post_exec_21x:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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stwu r5, -4(r1)
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mtlr r3
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mr r3, r6
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blrl
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lwz r5, 4(r1)
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stw r3, 0(r5)
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lwz r5, 0(r1)
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stw r4, 0(r5)
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lwz r0, 8(r1)
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addi r1, r1, 12
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mtlr r0
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blr
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/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
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ulong cr); */
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.global cpu_post_exec_31
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cpu_post_exec_31:
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isync
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mflr r0
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stwu r0, -4(r1)
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stwu r4, -4(r1)
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stwu r5, -4(r1)
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stwu r6, -4(r1)
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mtlr r3
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lwz r3, 0(r4)
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lwz r4, 0(r5)
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mr r6, r7
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mfcr r7
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blrl
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mtcr r7
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lwz r7, 8(r1)
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stw r3, 0(r7)
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lwz r7, 4(r1)
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stw r4, 0(r7)
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lwz r7, 0(r1)
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stw r5, 0(r7)
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lwz r0, 12(r1)
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addi r1, r1, 16
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mtlr r0
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blr
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/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
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.global cpu_post_complex_1_asm
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cpu_post_complex_1_asm:
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li r9,0
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cmpw r9,r7
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bge cpu_post_complex_1_done
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mtctr r7
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cpu_post_complex_1_loop:
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mullw r0,r3,r4
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subf r0,r5,r0
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divw r0,r0,r6
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add r9,r9,r0
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bdnz cpu_post_complex_1_loop
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cpu_post_complex_1_done:
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mr r3,r9
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blr
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/* int cpu_post_complex_2_asm (int x, int n); */
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.global cpu_post_complex_2_asm
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cpu_post_complex_2_asm:
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mr. r0,r4
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mtctr r0
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mr r0,r3
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li r3,1
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li r4,1
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blelr
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cpu_post_complex_2_loop:
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mullw r3,r3,r0
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add r3,r3,r4
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bdnz cpu_post_complex_2_loop
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blr
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#endif
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