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ba5eb2327b
Import misc cvmx-helper header files from 2013 U-Boot. They will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
129 lines
4.6 KiB
C
129 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*/
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#ifndef __CVMX_CONFIG_H__
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#define __CVMX_CONFIG_H__
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/************************* Config Specific Defines ************************/
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#define CVMX_LLM_NUM_PORTS 1
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/**< PKO queues per port for interface 0 (ports 0-15) */
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#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
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/**< PKO queues per port for interface 1 (ports 16-31) */
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#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
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/**< PKO queues per port for interface 4 (AGL) */
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#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE4 1
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/**< Limit on the number of PKO ports enabled for interface 0 */
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#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
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/**< Limit on the number of PKO ports enabled for interface 1 */
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#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
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/**< PKO queues per port for PCI (ports 32-35) */
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#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
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/**< PKO queues per port for Loop devices (ports 36-39) */
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#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
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/**< PKO queues per port for SRIO0 devices (ports 40-41) */
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#define CVMX_PKO_QUEUES_PER_PORT_SRIO0 1
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/**< PKO queues per port for SRIO1 devices (ports 42-43) */
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#define CVMX_PKO_QUEUES_PER_PORT_SRIO1 1
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/************************* FPA allocation *********************************/
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/* Pool sizes in bytes, must be multiple of a cache line */
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#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_3_SIZE (2 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_6_SIZE (8 * CVMX_CACHE_LINE_SIZE)
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#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
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/* Pools in use */
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/**< Packet buffers */
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#define CVMX_FPA_PACKET_POOL (0)
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#ifndef CVMX_FPA_PACKET_POOL_SIZE
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#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
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#endif
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/**< Work queue entries */
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#define CVMX_FPA_WQE_POOL (1)
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#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
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/**< PKO queue command buffers */
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#define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
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#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
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/**< BCH queue command buffers */
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#define CVMX_FPA_BCH_POOL (6)
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#define CVMX_FPA_BCH_POOL_SIZE CVMX_FPA_POOL6_SIZE
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/************************* FAU allocation ********************************/
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/* The fetch and add registers are allocated here. They are arranged
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* in order of descending size so that all alignment constraints are
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* automatically met.
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* The enums are linked so that the following enum continues allocating
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* where the previous one left off, so the numbering within each
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* enum always starts with zero. The macros take care of the address
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* increment size, so the values entered always increase by 1.
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* FAU registers are accessed with byte addresses.
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*/
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#define CVMX_FAU_REG_64_ADDR(x) (((x) << 3) + CVMX_FAU_REG_64_START)
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typedef enum {
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CVMX_FAU_REG_64_START = 0,
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/**< FAU registers for the position in PKO command buffers */
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CVMX_FAU_REG_OQ_ADDR_INDEX = CVMX_FAU_REG_64_ADDR(0),
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/* Array of 36 */
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CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(36),
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} cvmx_fau_reg_64_t;
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#define CVMX_FAU_REG_32_ADDR(x) (((x) << 2) + CVMX_FAU_REG_32_START)
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typedef enum {
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CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END,
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CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
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} cvmx_fau_reg_32_t;
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#define CVMX_FAU_REG_16_ADDR(x) (((x) << 1) + CVMX_FAU_REG_16_START)
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typedef enum {
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CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END,
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CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
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} cvmx_fau_reg_16_t;
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#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
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typedef enum {
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CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END,
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CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0),
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} cvmx_fau_reg_8_t;
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/* The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first available
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* FAU address that is not allocated in cvmx-config.h. This is 64 bit aligned.
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*/
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#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
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#define CVMX_FAU_REG_END (2048)
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/********************** scratch memory allocation *************************/
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/* Scratchpad memory allocation. Note that these are byte memory addresses.
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* Some uses of scratchpad (IOBDMA for example) require the use of 8-byte
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* aligned addresses, so proper alignment needs to be taken into account.
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*/
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/**< Pre allocation for PKO queue command buffers */
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#define CVMX_SCR_OQ_BUF_PRE_ALLOC (0)
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/**< Generic scratch iobdma area */
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#define CVMX_SCR_SCRATCH (8)
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/**< First location available after cvmx-config.h allocated region. */
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#define CVMX_SCR_REG_AVAIL_BASE (16)
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#endif /* __CVMX_CONFIG_H__ */
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