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CSSI has another CPU board, similar to the CMPC885 board that get plugged on the two base boards MCR3000_2G and MIAE. That CPU board is called CMPCPRO because it has a MPC8321E CPU, also known as Power QUICC II PRO. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
190 lines
4.2 KiB
Plaintext
190 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* CMPC885 Device Tree Source
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*
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* Copyright 2020 CS GROUP France
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*
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*/
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/dts-v1/;
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#include <dt-bindings/clk/mpc83xx-clk.h>
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/ {
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model = "CMPCPRO";
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compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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stdout-path = &serial0;
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};
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WDT: watchdog@0 {
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device_type = "watchdog";
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compatible = "fsl,pq1-wdt";
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};
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aliases {
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ethernet0 = ð0;
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etehrnet1 = ð1;
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8321@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <16384>; // L1, 16K
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i-cache-size = <16384>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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soc8321@b0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xb0000000 0x00100000>;
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reg = <0xb0000000 0x00000200>;
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bus-frequency = <0>;
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pmc: power@b00 {
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compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial0: serial@4500 {
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clocks = <&socclocks MPC83XX_CLK_CSB>;
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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ipic:pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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par_io@1400 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1400 0x100>;
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ranges;
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compatible = "fsl,mpc8323-qe-pario","simple-bus";
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device_type = "par_io";
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num-ports = <7>;
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qe_pio_a: gpio-controller@1400 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
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reg = <0x1400 0x18>;
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gpio-controller;
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};
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qe_pio_b: gpio-controller@1418 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
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reg = <0x1418 0x18>;
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gpio-controller;
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};
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qe_pio_c: gpio-controller@1430 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
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reg = <0x1430 0x18>;
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gpio-controller;
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};
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qe_pio_d: gpio-controller@1448 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
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reg = <0x1448 0x18>;
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gpio-controller;
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};
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};
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};
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socclocks: clocks {
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bootph-all;
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compatible = "fsl,mpc832x-clk";
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#clock-cells = <1>;
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};
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qe@b0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe","simple-bus";
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ranges = <0x0 0xb0100000 0x00100000>;
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reg = <0xb0100000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <198000000>;
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fsl,qe-num-riscs = <1>;
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fsl,qe-num-snums = <28>;
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spi@4c0 {
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clocks = <&socclocks MPC83XX_CLK_CSB>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,mpc832x-spi";
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reg = <0x4c0 0x40>;
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mode = "cpu";
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gpios = <&qe_pio_d 3 1>;
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clock-frequency = <0>;
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eeprom@3 {
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compatible = "atmel,at25", "cs,eeprom";
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cell-index = <1>;
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};
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};
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eth0: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <2>;
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reg = <0x3000 0x200>;
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rx-clock-name = "clk17";
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tx-clock-name = "clk17";
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phy-handle = <&phy1>;
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phy-connection-type = "rmii";
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};
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eth1: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <3>;
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reg = <0x2200 0x200>;
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rx-clock-name = "clk12";
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tx-clock-name = "clk12";
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phy-handle = <&phy2>;
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phy-connection-type = "rmii";
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};
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mdio@3120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3120 0x18>;
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compatible = "fsl,ucc-mdio";
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phy1:ethernet-phy@1 {
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interrupt-parent = <&ipic>;
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reg = <0x1>;
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interrupts = <17 8>;
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device_type = "ethernet-phy";
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};
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phy2:ethernet-phy@2 {
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interrupt-parent = <&ipic>;
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reg = <0x2>;
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interrupts = <17 8>;
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device_type = "ethernet-phy";
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};
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};
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};
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};
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