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	Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
		
			
				
	
	
		
			72 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			72 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2004, 2007 Freescale Semiconductor.
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|  * Copyright(c) 2003 Motorola Inc.
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|  */
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| 
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| #ifndef	__MPC85xx_H__
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| #define __MPC85xx_H__
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| 
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| /* define for common ppc_asm.tmpl */
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| #define EXC_OFF_SYS_RESET	0x100	/* System reset */
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| #define _START_OFFSET		0
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| 
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| #if defined(CONFIG_E500)
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| #include <e500.h>
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| #endif
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| 
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| /*
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|  * SCCR - System Clock Control Register, 9-8
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|  */
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| #define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
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| #define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
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| #define SCCR_DFBRG_SHIFT 0
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| 
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| #define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
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| #define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
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| #define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
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| #define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
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| 
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| /*
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|  * Define default values for some CCSR macros to make header files cleaner*
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|  *
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|  * To completely disable CCSR relocation in a board header file, define
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|  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
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|  * to a value that is the same as CONFIG_SYS_CCSRBAR.
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|  */
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| 
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| #ifdef CONFIG_SYS_CCSRBAR_PHYS
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| #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
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| CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
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| #endif
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| 
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| #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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| #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
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| #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
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| #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
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| #endif
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| 
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| #ifndef CONFIG_SYS_CCSRBAR
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| #define CONFIG_SYS_CCSRBAR 		CONFIG_SYS_CCSRBAR_DEFAULT
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| #endif
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| 
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| #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
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| #ifdef CONFIG_PHYS_64BIT
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| #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
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| #else
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| #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
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| #endif
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| #endif
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| 
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| #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
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| #define CONFIG_SYS_CCSRBAR_PHYS_LOW 	CONFIG_SYS_CCSRBAR_DEFAULT
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| #endif
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| 
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| #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
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| 				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
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| 
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| #ifndef CONFIG_SYS_IMMR
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| #define CONFIG_SYS_IMMR 		CONFIG_SYS_CCSRBAR
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| #endif
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| 
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| #endif	/* __MPC85xx_H__ */
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