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95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/*
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* (C) Copyright 2008
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* Grazvydas Ignotas <notasas@gmail.com>
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*
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* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include "pandora.h"
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
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gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
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gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
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gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
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power_init_r();
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/* Configure GPIOs to output */
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writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
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writel(~GPIO22, &gpio4_base->oe); /* 118 */
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writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31),
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&gpio5_base->oe); /* 128, 129, 156-159 */
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writel(~GPIO4, &gpio6_base->oe); /* 164 */
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/* Set GPIOs */
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writel(GPIO28, &gpio5_base->setdataout);
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writel(GPIO4, &gpio6_base->setdataout);
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_PANDORA();
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}
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