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a152234752
Import cvmx-mio-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
354 lines
8.1 KiB
C
354 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_MIO_DEFS_H__
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#define __CVMX_MIO_DEFS_H__
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#define CVMX_MIO_PTP_CLOCK_CFG (0x0001070000000F00ull)
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#define CVMX_MIO_PTP_EVT_CNT (0x0001070000000F28ull)
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#define CVMX_MIO_RST_BOOT (0x0001180000001600ull)
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#define CVMX_MIO_RST_CTLX(offset) (0x0001180000001618ull + ((offset) & 1))
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#define CVMX_MIO_QLMX_CFG(offset) (0x0001180000001590ull + ((offset) & 7) * 8)
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/**
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* cvmx_mio_ptp_clock_cfg
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*
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* This register configures the timestamp architecture.
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*
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*/
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union cvmx_mio_ptp_clock_cfg {
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u64 u64;
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struct cvmx_mio_ptp_clock_cfg_s {
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u64 reserved_40_63 : 24;
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u64 ext_clk_edge : 2;
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u64 ckout_out4 : 1;
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u64 pps_out : 5;
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u64 pps_inv : 1;
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u64 pps_en : 1;
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u64 ckout_out : 4;
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u64 ckout_inv : 1;
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u64 ckout_en : 1;
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u64 evcnt_in : 6;
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u64 evcnt_edge : 1;
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u64 evcnt_en : 1;
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u64 tstmp_in : 6;
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u64 tstmp_edge : 1;
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u64 tstmp_en : 1;
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u64 ext_clk_in : 6;
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u64 ext_clk_en : 1;
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u64 ptp_en : 1;
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} s;
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struct cvmx_mio_ptp_clock_cfg_cn61xx {
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u64 reserved_42_63 : 22;
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u64 pps : 1;
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u64 ckout : 1;
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u64 ext_clk_edge : 2;
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u64 ckout_out4 : 1;
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u64 pps_out : 5;
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u64 pps_inv : 1;
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u64 pps_en : 1;
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u64 ckout_out : 4;
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u64 ckout_inv : 1;
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u64 ckout_en : 1;
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u64 evcnt_in : 6;
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u64 evcnt_edge : 1;
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u64 evcnt_en : 1;
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u64 tstmp_in : 6;
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u64 tstmp_edge : 1;
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u64 tstmp_en : 1;
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u64 ext_clk_in : 6;
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u64 ext_clk_en : 1;
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u64 ptp_en : 1;
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} cn61xx;
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struct cvmx_mio_ptp_clock_cfg_cn63xx {
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u64 reserved_24_63 : 40;
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u64 evcnt_in : 6;
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u64 evcnt_edge : 1;
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u64 evcnt_en : 1;
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u64 tstmp_in : 6;
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u64 tstmp_edge : 1;
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u64 tstmp_en : 1;
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u64 ext_clk_in : 6;
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u64 ext_clk_en : 1;
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u64 ptp_en : 1;
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} cn63xx;
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struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
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struct cvmx_mio_ptp_clock_cfg_s cn66xx;
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struct cvmx_mio_ptp_clock_cfg_cn61xx cn68xx;
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struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
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struct cvmx_mio_ptp_clock_cfg_cn70xx {
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u64 reserved_42_63 : 22;
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u64 ckout : 1;
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u64 pps : 1;
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u64 ext_clk_edge : 2;
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u64 reserved_32_37 : 6;
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u64 pps_inv : 1;
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u64 pps_en : 1;
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u64 reserved_26_29 : 4;
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u64 ckout_inv : 1;
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u64 ckout_en : 1;
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u64 evcnt_in : 6;
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u64 evcnt_edge : 1;
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u64 evcnt_en : 1;
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u64 tstmp_in : 6;
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u64 tstmp_edge : 1;
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u64 tstmp_en : 1;
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u64 ext_clk_in : 6;
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u64 ext_clk_en : 1;
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u64 ptp_en : 1;
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} cn70xx;
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struct cvmx_mio_ptp_clock_cfg_cn70xx cn70xxp1;
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struct cvmx_mio_ptp_clock_cfg_cn70xx cn73xx;
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struct cvmx_mio_ptp_clock_cfg_cn70xx cn78xx;
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struct cvmx_mio_ptp_clock_cfg_cn70xx cn78xxp1;
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struct cvmx_mio_ptp_clock_cfg_cn61xx cnf71xx;
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struct cvmx_mio_ptp_clock_cfg_cn70xx cnf75xx;
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};
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typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;
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/**
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* cvmx_mio_ptp_evt_cnt
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*
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* This register contains the PTP event counter.
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*
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*/
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union cvmx_mio_ptp_evt_cnt {
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u64 u64;
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struct cvmx_mio_ptp_evt_cnt_s {
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u64 cntr : 64;
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} s;
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struct cvmx_mio_ptp_evt_cnt_s cn61xx;
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struct cvmx_mio_ptp_evt_cnt_s cn63xx;
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struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
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struct cvmx_mio_ptp_evt_cnt_s cn66xx;
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struct cvmx_mio_ptp_evt_cnt_s cn68xx;
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struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
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struct cvmx_mio_ptp_evt_cnt_s cn70xx;
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struct cvmx_mio_ptp_evt_cnt_s cn70xxp1;
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struct cvmx_mio_ptp_evt_cnt_s cn73xx;
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struct cvmx_mio_ptp_evt_cnt_s cn78xx;
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struct cvmx_mio_ptp_evt_cnt_s cn78xxp1;
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struct cvmx_mio_ptp_evt_cnt_s cnf71xx;
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struct cvmx_mio_ptp_evt_cnt_s cnf75xx;
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};
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typedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t;
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/**
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* cvmx_mio_rst_boot
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*
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* Notes:
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* JTCSRDIS, EJTAGDIS, ROMEN reset to 1 in authentik mode; in all other modes they reset to 0.
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*
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*/
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union cvmx_mio_rst_boot {
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u64 u64;
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struct cvmx_mio_rst_boot_s {
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u64 chipkill : 1;
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u64 jtcsrdis : 1;
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u64 ejtagdis : 1;
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u64 romen : 1;
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u64 ckill_ppdis : 1;
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u64 jt_tstmode : 1;
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u64 reserved_50_57 : 8;
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u64 lboot_ext : 2;
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u64 reserved_44_47 : 4;
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u64 qlm4_spd : 4;
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u64 qlm3_spd : 4;
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u64 c_mul : 6;
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u64 pnr_mul : 6;
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u64 qlm2_spd : 4;
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u64 qlm1_spd : 4;
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u64 qlm0_spd : 4;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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} s;
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struct cvmx_mio_rst_boot_cn61xx {
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u64 chipkill : 1;
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u64 jtcsrdis : 1;
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u64 ejtagdis : 1;
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u64 romen : 1;
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u64 ckill_ppdis : 1;
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u64 jt_tstmode : 1;
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u64 reserved_50_57 : 8;
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u64 lboot_ext : 2;
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u64 reserved_36_47 : 12;
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u64 c_mul : 6;
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u64 pnr_mul : 6;
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u64 qlm2_spd : 4;
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u64 qlm1_spd : 4;
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u64 qlm0_spd : 4;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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} cn61xx;
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struct cvmx_mio_rst_boot_cn63xx {
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u64 reserved_36_63 : 28;
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u64 c_mul : 6;
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u64 pnr_mul : 6;
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u64 qlm2_spd : 4;
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u64 qlm1_spd : 4;
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u64 qlm0_spd : 4;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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} cn63xx;
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struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
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struct cvmx_mio_rst_boot_cn66xx {
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u64 chipkill : 1;
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u64 jtcsrdis : 1;
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u64 ejtagdis : 1;
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u64 romen : 1;
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u64 ckill_ppdis : 1;
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u64 reserved_50_58 : 9;
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u64 lboot_ext : 2;
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u64 reserved_36_47 : 12;
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u64 c_mul : 6;
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u64 pnr_mul : 6;
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u64 qlm2_spd : 4;
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u64 qlm1_spd : 4;
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u64 qlm0_spd : 4;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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} cn66xx;
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struct cvmx_mio_rst_boot_cn68xx {
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u64 reserved_59_63 : 5;
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u64 jt_tstmode : 1;
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u64 reserved_44_57 : 14;
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u64 qlm4_spd : 4;
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u64 qlm3_spd : 4;
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u64 c_mul : 6;
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u64 pnr_mul : 6;
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u64 qlm2_spd : 4;
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u64 qlm1_spd : 4;
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u64 qlm0_spd : 4;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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} cn68xx;
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struct cvmx_mio_rst_boot_cn68xxp1 {
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u64 reserved_44_63 : 20;
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u64 qlm4_spd : 4;
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u64 qlm3_spd : 4;
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u64 c_mul : 6;
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u64 pnr_mul : 6;
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u64 qlm2_spd : 4;
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u64 qlm1_spd : 4;
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u64 qlm0_spd : 4;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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} cn68xxp1;
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struct cvmx_mio_rst_boot_cn61xx cnf71xx;
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};
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typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t;
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/**
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* cvmx_mio_rst_ctl#
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*
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* Notes:
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* GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz.
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* GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz.
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*/
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union cvmx_mio_rst_ctlx {
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u64 u64;
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struct cvmx_mio_rst_ctlx_s {
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u64 reserved_13_63 : 51;
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u64 in_rev_ln : 1;
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u64 rev_lanes : 1;
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u64 gen1_only : 1;
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u64 prst_link : 1;
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u64 rst_done : 1;
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u64 rst_link : 1;
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u64 host_mode : 1;
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u64 prtmode : 2;
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u64 rst_drv : 1;
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u64 rst_rcv : 1;
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u64 rst_chip : 1;
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u64 rst_val : 1;
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} s;
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struct cvmx_mio_rst_ctlx_s cn61xx;
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struct cvmx_mio_rst_ctlx_cn63xx {
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u64 reserved_10_63 : 54;
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u64 prst_link : 1;
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u64 rst_done : 1;
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u64 rst_link : 1;
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u64 host_mode : 1;
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u64 prtmode : 2;
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u64 rst_drv : 1;
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u64 rst_rcv : 1;
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u64 rst_chip : 1;
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u64 rst_val : 1;
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} cn63xx;
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struct cvmx_mio_rst_ctlx_cn63xxp1 {
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u64 reserved_9_63 : 55;
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u64 rst_done : 1;
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u64 rst_link : 1;
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u64 host_mode : 1;
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u64 prtmode : 2;
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u64 rst_drv : 1;
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u64 rst_rcv : 1;
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u64 rst_chip : 1;
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u64 rst_val : 1;
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} cn63xxp1;
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struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
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struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
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struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
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struct cvmx_mio_rst_ctlx_s cnf71xx;
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};
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typedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t;
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/**
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* cvmx_mio_qlm#_cfg
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*
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* Notes:
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* Certain QLM_SPD is valid only for certain QLM_CFG configuration, refer to HRM for valid
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* combinations. These csrs are reset only on COLD_RESET. The Reset values for QLM_SPD and QLM_CFG
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* are as follows: MIO_QLM0_CFG SPD=F, CFG=2 SGMII (AGX0)
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* MIO_QLM1_CFG SPD=0, CFG=1 PCIE 2x1 (PEM0/PEM1)
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*/
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union cvmx_mio_qlmx_cfg {
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u64 u64;
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struct cvmx_mio_qlmx_cfg_s {
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u64 reserved_15_63 : 49;
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u64 prtmode : 1;
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u64 reserved_12_13 : 2;
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u64 qlm_spd : 4;
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u64 reserved_4_7 : 4;
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u64 qlm_cfg : 4;
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} s;
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struct cvmx_mio_qlmx_cfg_cn61xx {
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u64 reserved_15_63 : 49;
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u64 prtmode : 1;
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u64 reserved_12_13 : 2;
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u64 qlm_spd : 4;
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u64 reserved_2_7 : 6;
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u64 qlm_cfg : 2;
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} cn61xx;
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struct cvmx_mio_qlmx_cfg_cn66xx {
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u64 reserved_12_63 : 52;
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u64 qlm_spd : 4;
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u64 reserved_4_7 : 4;
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u64 qlm_cfg : 4;
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} cn66xx;
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struct cvmx_mio_qlmx_cfg_cn68xx {
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u64 reserved_12_63 : 52;
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u64 qlm_spd : 4;
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u64 reserved_3_7 : 5;
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u64 qlm_cfg : 3;
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} cn68xx;
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struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
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struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx;
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};
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typedef union cvmx_mio_qlmx_cfg cvmx_mio_qlmx_cfg_t;
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#endif
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