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302 lines
7.0 KiB
C
302 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <dm.h>
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#include <uboot_aes.h>
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#include <asm/io.h>
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#include <asm/arch/aes.h>
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#include <asm/arch/otp.h>
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#include <malloc.h>
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#define ONE_SECOND 0xC00000
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struct npcm_aes_priv {
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struct npcm_aes_regs *regs;
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};
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static struct npcm_aes_priv *aes_priv;
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static u8 fkeyind_to_set = 0xff;
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static int second_timeout(u32 *addr, u32 bitmask, u32 bitpol)
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{
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ulong time, i = 0;
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time = get_timer(0);
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/* default 1 second timeout */
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while (((readl(addr) & bitmask) == bitpol) && i < ONE_SECOND)
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i++;
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if (i == ONE_SECOND) {
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printf("%xms timeout: addr = %x, mask = %x\n", (u32)get_timer(time),
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*addr, bitmask);
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return -1;
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}
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return 0;
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}
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int npcm_aes_select_key(u8 fkeyind)
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{
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if (npcm_otp_is_fuse_array_disabled(NPCM_KEY_SA)) {
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printf("AES key access denied\n");
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return -EACCES;
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}
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if (fkeyind < 4)
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fkeyind_to_set = fkeyind;
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return 0;
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}
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static int npcm_aes_init(u8 dec_enc)
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{
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struct npcm_aes_regs *regs = aes_priv->regs;
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u32 ctrl, orgctrlval, wrtimeout;
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/* reset hw */
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writel(readl(®s->aes_sw_reset) | SW_RESET_BIT, ®s->aes_sw_reset);
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writel(readl(®s->aes_fifo_status) | DIN_FIFO_OVERFLOW, ®s->aes_fifo_status);
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writel(readl(®s->aes_fifo_status) | DOUT_FIFO_UNDERFLOW, ®s->aes_fifo_status);
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/* Workaround to over come Errata #648 */
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orgctrlval = readl(®s->aes_control);
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ctrl = (0x00002004 | dec_enc); /* AES256(CBC) */
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if (ctrl != orgctrlval) {
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writel(ctrl, ®s->aes_control);
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if (ctrl != readl(®s->aes_control)) {
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u32 read_ctrl;
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int intwr;
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for (wrtimeout = 0; wrtimeout < 1000; wrtimeout++) {
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for (intwr = 0 ; intwr < 10; intwr++) {
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writel(ctrl, ®s->aes_control);
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writew(ctrl, (u16 *)®s->aes_control + 1);
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/* Write configurable info in a single write operation */
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mb();
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}
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read_ctrl = readl(®s->aes_control);
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if (ctrl == read_ctrl)
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break;
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}
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if (wrtimeout == 1000) {
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printf("\nTIMEOUT expected data=0x%x Actual AES_CONTROL data 0x%x\n\n",
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ctrl, read_ctrl);
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return -EAGAIN;
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}
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printf("Workaround success, wrtimeout = %d\n", wrtimeout);
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}
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}
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if (second_timeout(®s->aes_busy, AES_BUSY_BIT, AES_BUSY_BIT))
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return -EAGAIN;
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return 0;
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}
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static inline void npcm_aes_load_iv(u8 *iv)
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{
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struct npcm_aes_regs *regs = aes_priv->regs;
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u32 *p = (u32 *)iv;
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u32 i;
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/* Initialization Vector is loaded in 32-bit chunks */
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for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++)
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writel(p[i], ®s->aes_iv_0 + i);
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}
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static inline void npcm_aes_load_key(u8 *key)
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{
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struct npcm_aes_regs *regs = aes_priv->regs;
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u32 *p = (u32 *)key;
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u32 i;
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/* The key can be loaded either via the configuration or by using sideband
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* key port (aes_select_key).
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* If aes_select_key has been called ('fkeyind_to_set' was set to desired
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* key index) and no key is specified (key is NULL), we should use the
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* key index. Otherwise, we write the given key to the registers.
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*/
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if (!key && fkeyind_to_set < 4) {
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npcm_otp_select_key(fkeyind_to_set);
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/* Sample the new key */
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writel(readl(®s->aes_sk) | AES_SK_BIT, ®s->aes_sk);
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} else {
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/* Initialization Vector is loaded in 32-bit chunks */
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for (i = 0; i < (2 * SIZE_AES_BLOCK / sizeof(u32)); i++)
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writel(p[i], ®s->aes_key_0 + i);
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fkeyind_to_set = 0xff;
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}
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}
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static inline void npcm_aes_write(u32 *in)
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{
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struct npcm_aes_regs *regs = aes_priv->regs;
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u32 i;
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/* 16 Byte AES Block is written in 32-bit chunks */
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for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++)
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writel(in[i], ®s->aes_fifo_data);
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}
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static inline void npcm_aes_read(u32 *out)
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{
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struct npcm_aes_regs *regs = aes_priv->regs;
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u32 i;
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/* Data is read in 32-bit chunks */
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for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++)
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out[i] = readl(®s->aes_fifo_data);
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}
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static void npcm_aes_feed(u32 num_aes_blocks, u32 *datain, u32 *dataout)
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{
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struct npcm_aes_regs *regs = aes_priv->regs;
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u32 aes_datablk;
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u32 total_blocks = num_aes_blocks;
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u32 blocks_left = num_aes_blocks;
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/* data mode */
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writel(readl(®s->aes_busy) | AES_BUSY_BIT, ®s->aes_busy);
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/* Clear overflow and underflow */
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writel(readl(®s->aes_fifo_status) | DIN_FIFO_OVERFLOW, ®s->aes_fifo_status);
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writel(readl(®s->aes_fifo_status) | DOUT_FIFO_UNDERFLOW, ®s->aes_fifo_status);
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/* datain/dataout is advanced in 32-bit chunks */
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aes_datablk = (SIZE_AES_BLOCK / sizeof(u32));
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/* Quit if there is no complete blocks */
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if (total_blocks == 0)
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return;
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/* Write the first block */
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if (total_blocks > 1) {
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npcm_aes_write(datain);
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datain += aes_datablk;
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blocks_left--;
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}
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/* Write the second block */
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if (total_blocks > 2) {
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second_timeout(®s->aes_fifo_status, DIN_FIFO_EMPTY, 0);
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npcm_aes_write(datain);
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datain += aes_datablk;
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blocks_left--;
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}
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/* Write & read available blocks */
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while (blocks_left > 0) {
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second_timeout(®s->aes_fifo_status, DIN_FIFO_FULL, DIN_FIFO_FULL);
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/* Write next block */
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npcm_aes_write(datain);
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datain += aes_datablk;
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/* Wait till DOUT FIFO is empty */
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second_timeout(®s->aes_fifo_status, DOUT_FIFO_EMPTY, DOUT_FIFO_EMPTY);
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/* Read next block */
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npcm_aes_read(dataout);
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dataout += aes_datablk;
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blocks_left--;
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}
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if (total_blocks > 2) {
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second_timeout(®s->aes_fifo_status, DOUT_FIFO_FULL, 0);
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/* Read next block */
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npcm_aes_read(dataout);
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dataout += aes_datablk;
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second_timeout(®s->aes_fifo_status, DOUT_FIFO_FULL, 0);
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/* Read next block */
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npcm_aes_read(dataout);
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dataout += aes_datablk;
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} else if (total_blocks > 1) {
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second_timeout(®s->aes_fifo_status, DOUT_FIFO_FULL, 0);
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/* Read next block */
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npcm_aes_read(dataout);
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dataout += aes_datablk;
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}
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}
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void aes_expand_key(u8 *key, u32 key_size, u8 *expkey)
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{
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/* npcm hw expands the key automatically, just copy it */
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memcpy(expkey, key, SIZE_AES_BLOCK * 2);
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}
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void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
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u32 num_aes_blocks)
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{
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if (npcm_aes_init(AES_OP_ENCRYPT))
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return;
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npcm_aes_load_iv(iv);
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npcm_aes_load_key(key_exp);
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npcm_aes_feed(num_aes_blocks, (u32 *)src, (u32 *)dst);
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}
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void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
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u32 num_aes_blocks)
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{
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if (npcm_aes_init(AES_OP_DECRYPT))
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return;
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npcm_aes_load_iv(iv);
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npcm_aes_load_key(key_exp);
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npcm_aes_feed(num_aes_blocks, (u32 *)src, (u32 *)dst);
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}
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static int npcm_aes_bind(struct udevice *dev)
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{
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aes_priv = calloc(1, sizeof(struct npcm_aes_priv));
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if (!aes_priv) {
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printf("%s: %d\n", __func__, __LINE__);
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return -ENOMEM;
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}
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aes_priv->regs = dev_read_addr_ptr(dev);
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if (!aes_priv->regs) {
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printf("Cannot find aes reg address, binding failed\n");
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return -EINVAL;
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}
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printf("AES: NPCM AES module bind OK\n");
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return 0;
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}
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static const struct udevice_id npcm_aes_ids[] = {
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{ .compatible = "nuvoton,npcm845-aes" },
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{ .compatible = "nuvoton,npcm750-aes" },
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{ }
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};
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U_BOOT_DRIVER(npcm_aes) = {
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.name = "npcm_aes",
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.id = UCLASS_MISC,
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.of_match = npcm_aes_ids,
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.priv_auto = sizeof(struct npcm_aes_priv),
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.bind = npcm_aes_bind,
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};
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