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d926695cc5
Display Port (DP) has own dma driver that's why add this skeleton driver only for handling power domain setting and send configuration object to PMUFW to enable it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/fe8bc313bcd430b04e9fa6fb770d5799ef28b350.1645627920.git.michal.simek@xilinx.com
44 lines
859 B
C
44 lines
859 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Xilinx Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dma.h>
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#include <dma-uclass.h>
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#include <errno.h>
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#include <dm/device_compat.h>
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/**
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* struct zynqmp_dpdma_priv - Private structure
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* @dev: Device uclass for video_ops
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*/
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struct zynqmp_dpdma_priv {
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struct udevice *dev;
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};
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static int zynqmp_dpdma_probe(struct udevice *dev)
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{
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/* Only placeholder for power domain driver */
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return 0;
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}
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static const struct dma_ops zynqmp_dpdma_ops = {
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};
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static const struct udevice_id zynqmp_dpdma_ids[] = {
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{ .compatible = "xlnx,zynqmp-dpdma" },
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{ }
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};
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U_BOOT_DRIVER(zynqmp_dpdma) = {
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.name = "zynqmp_dpdma",
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.id = UCLASS_DMA,
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.of_match = zynqmp_dpdma_ids,
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.ops = &zynqmp_dpdma_ops,
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.probe = zynqmp_dpdma_probe,
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.priv_auto = sizeof(struct zynqmp_dpdma_priv),
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};
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