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019df879a9
The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <libfdt.h>
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#include <linux/kernel.h>
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#include <mach/init.h>
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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static const struct uniphier_board_data ph1_sld3_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x20000000,
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.dram_ch0_width = 32,
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.dram_ch1_base = 0xc0000000,
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.dram_ch1_size = 0x20000000,
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.dram_ch1_width = 16,
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.dram_ch2_base = 0xc0000000,
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.dram_ch2_size = 0x10000000,
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.dram_ch2_width = 16,
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.dram_freq = 1600,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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static const struct uniphier_board_data ph1_ld4_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x10000000,
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.dram_ch0_width = 16,
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.dram_ch1_base = 0x90000000,
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.dram_ch1_size = 0x10000000,
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.dram_ch1_width = 16,
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.dram_freq = 1600,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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static const struct uniphier_board_data ph1_pro4_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x20000000,
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.dram_ch0_width = 32,
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.dram_ch1_base = 0xa0000000,
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.dram_ch1_size = 0x20000000,
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.dram_ch1_width = 32,
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.dram_freq = 1600,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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static const struct uniphier_board_data ph1_sld8_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x10000000,
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.dram_ch0_width = 16,
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.dram_ch1_base = 0x90000000,
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.dram_ch1_size = 0x10000000,
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.dram_ch1_width = 16,
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.dram_freq = 1333,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
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static const struct uniphier_board_data ph1_pro5_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x20000000,
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.dram_ch0_width = 32,
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.dram_ch1_base = 0xa0000000,
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.dram_ch1_size = 0x20000000,
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.dram_ch1_width = 32,
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.dram_freq = 1866,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
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defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
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static const struct uniphier_board_data proxstream2_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x40000000,
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.dram_ch0_width = 32,
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.dram_ch1_base = 0xc0000000,
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.dram_ch1_size = 0x20000000,
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.dram_ch1_width = 32,
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.dram_ch2_base = 0xe0000000,
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.dram_ch2_size = 0x20000000,
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.dram_ch2_width = 16,
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.dram_freq = 1866,
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};
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#endif
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struct uniphier_board_id {
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const char *compatible;
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const struct uniphier_board_data *param;
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};
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static const struct uniphier_board_id uniphier_boards[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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{ "socionext,ph1-sld3", &ph1_sld3_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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{ "socionext,ph1-ld4", &ph1_ld4_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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{ "socionext,ph1-pro4", &ph1_pro4_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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{ "socionext,ph1-sld8", &ph1_sld8_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
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{ "socionext,ph1-pro5", &ph1_pro5_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
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{ "socionext,proxstream2", &proxstream2_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
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{ "socionext,ph1-ld6b", &proxstream2_data, },
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#endif
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};
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const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
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if (!fdt_node_check_compatible(fdt, 0,
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uniphier_boards[i].compatible))
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return uniphier_boards[i].param;
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}
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return NULL;
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}
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