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f132c4967e
This patchset has following changes: - introduce stm32h750.dtsi to support stm32h750 value line - add pin groups for usart3/uart4/spi1/sdmmc2 - add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile) - add stm32h750i-art-pi.dts to support art-pi board - add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot) art-pi board component: - 8MiB qspi flash - 16MiB spi flash - 32MiB sdram - ap6212 wifi&bt&fm the detail board information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
49 lines
995 B
C
49 lines
995 B
C
#ifndef DT_BINDINGS_STM32_SDRAM_H
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#define DT_BINDINGS_STM32_SDRAM_H
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#define NO_COL_8 0x0
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#define NO_COL_9 0x1
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#define NO_COL_10 0x2
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#define NO_COL_11 0x3
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#define NO_ROW_11 0x0
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#define NO_ROW_12 0x1
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#define NO_ROW_13 0x2
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#define MWIDTH_8 0x0
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#define MWIDTH_16 0x1
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#define MWIDTH_32 0x2
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#define BANKS_2 0x0
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#define BANKS_4 0x1
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#define CAS_1 0x1
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#define CAS_2 0x2
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#define CAS_3 0x3
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#define SDCLK_DIS 0x0
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#define SDCLK_2 0x2
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#define SDCLK_3 0x3
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#define RD_BURST_EN 0x1
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#define RD_BURST_DIS 0x0
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#define RD_PIPE_DL_0 0x0
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#define RD_PIPE_DL_1 0x1
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#define RD_PIPE_DL_2 0x2
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/* Timing = value +1 cycles */
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#define TMRD_1 (1 - 1)
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#define TMRD_2 (2 - 1)
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#define TMRD_3 (3 - 1)
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#define TXSR_1 (1 - 1)
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#define TXSR_6 (6 - 1)
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#define TXSR_7 (7 - 1)
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#define TXSR_8 (8 - 1)
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#define TRAS_1 (1 - 1)
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#define TRAS_4 (4 - 1)
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#define TRAS_6 (6 - 1)
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#define TRC_6 (6 - 1)
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#define TWR_1 (1 - 1)
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#define TWR_2 (2 - 1)
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#define TRP_2 (2 - 1)
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#define TRCD_1 (1 - 1)
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#define TRCD_2 (2 - 1)
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#endif
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