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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
95 lines
1.8 KiB
C
95 lines
1.8 KiB
C
/*
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* Copyright (c) 2012 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/i8254.h>
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#include <asm/ibmpc.h>
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#include <asm/msr.h>
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#include <asm/u-boot-x86.h>
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DECLARE_GLOBAL_DATA_PTR;
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void timer_set_base(u64 base)
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{
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gd->arch.tsc_base = base;
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}
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/*
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* Get the number of CPU time counter ticks since it was read first time after
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* restart. This yields a free running counter guaranteed to take almost 6
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* years to wrap around even at 100GHz clock rate.
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*/
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u64 __attribute__((no_instrument_function)) get_ticks(void)
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{
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u64 now_tick = rdtsc();
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/* We assume that 0 means the base hasn't been set yet */
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if (!gd->arch.tsc_base)
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panic("No tick base available");
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return now_tick - gd->arch.tsc_base;
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}
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#define PLATFORM_INFO_MSR 0xce
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/* Get the speed of the TSC timer in MHz */
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unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
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{
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u32 ratio;
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u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
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/* 100MHz times Max Non Turbo ratio */
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ratio = (platform_info >> 8) & 0xff;
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return 100 * ratio;
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}
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unsigned long get_tbclk(void)
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{
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return get_tbclk_mhz() * 1000 * 1000;
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}
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static ulong get_ms_timer(void)
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{
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return (get_ticks() * 1000) / get_tbclk();
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}
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ulong get_timer(ulong base)
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{
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return get_ms_timer() - base;
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}
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ulong __attribute__((no_instrument_function)) timer_get_us(void)
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{
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return get_ticks() / get_tbclk_mhz();
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}
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ulong timer_get_boot_us(void)
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{
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return timer_get_us();
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}
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void __udelay(unsigned long usec)
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{
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u64 now = get_ticks();
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u64 stop;
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stop = now + usec * get_tbclk_mhz();
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while ((int64_t)(stop - get_ticks()) > 0)
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;
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}
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int timer_init(void)
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{
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#ifdef CONFIG_SYS_PCAT_TIMER
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/* Set up the PCAT timer if required */
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pcat_timer_init();
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#endif
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return 0;
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}
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