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155 lines
3.7 KiB
C
155 lines
3.7 KiB
C
/*
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* (C) Copyright 2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND)
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#include <asm/processor.h>
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#include <nand.h>
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struct alpr_ndfc_regs {
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u8 cmd[4];
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u8 addr_wait;
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u8 term;
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u8 dummy;
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u8 dummy2;
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u8 data;
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};
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static u8 hwctl;
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static struct alpr_ndfc_regs *alpr_ndfc = NULL;
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#define readb(addr) (u8)(*(volatile u8 *)(addr))
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#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
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/*
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* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
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* the NAND devices. The NDFC has command, address and data registers that
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* when accessed will set up the NAND flash pins appropriately. We'll use the
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* hwcontrol function to save the configuration in a global variable.
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* We can then use this information in the read and write functions to
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* determine which NDFC register to access.
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*
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* There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
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*/
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static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE )
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hwctl |= 0x1;
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else
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hwctl &= ~0x1;
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if ( ctrl & NAND_ALE )
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hwctl |= 0x2;
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else
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hwctl &= ~0x2;
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if ( (ctrl & NAND_NCE) != NAND_NCE)
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writeb(0x00, &(alpr_ndfc->term));
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static u_char alpr_nand_read_byte(struct mtd_info *mtd)
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{
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return readb(&(alpr_ndfc->data));
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}
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static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct nand_chip *nand = mtd->priv;
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int i;
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for (i = 0; i < len; i++) {
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if (hwctl & 0x1)
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/*
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* IO_ADDR_W used as CMD[i] reg to support multiple NAND
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* chips.
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*/
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writeb(buf[i], nand->IO_ADDR_W);
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else if (hwctl & 0x2)
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writeb(buf[i], &(alpr_ndfc->addr_wait));
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else
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writeb(buf[i], &(alpr_ndfc->data));
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}
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}
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static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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buf[i] = readb(&(alpr_ndfc->data));
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}
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}
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static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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if (buf[i] != readb(&(alpr_ndfc->data)))
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return i;
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return 0;
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}
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static int alpr_nand_dev_ready(struct mtd_info *mtd)
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{
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volatile u_char val;
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/*
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* Blocking read to wait for NAND to be ready
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*/
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val = readb(&(alpr_ndfc->addr_wait));
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/*
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* Return always true
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*/
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return 1;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
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nand->ecc.mode = NAND_ECC_SOFT;
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/* Reference hardware control function */
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nand->cmd_ctrl = alpr_nand_hwcontrol;
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nand->read_byte = alpr_nand_read_byte;
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nand->write_buf = alpr_nand_write_buf;
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nand->read_buf = alpr_nand_read_buf;
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nand->verify_buf = alpr_nand_verify_buf;
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nand->dev_ready = alpr_nand_dev_ready;
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return 0;
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}
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#endif
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