mirror of
https://github.com/smaeul/u-boot.git
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411 lines
11 KiB
C
411 lines
11 KiB
C
/*
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <ds1722.h>
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#include <asm/io.h>
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#include <asm/ic/sc520.h>
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#include <asm/ic/ssi.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Theory:
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* We first set up all IRQs to be non-pci, edge triggered,
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* when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
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* called we reallocate irqs to the pci bus with sc520_pci_set_irq()
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* as needed. Whe choose the irqs to gram from a configurable list
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* inside pci_sc520_fixup_irq() (If this list contains stupid irq's
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* such as 0 thngas will not work)
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*/
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static void irq_init(void)
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{
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/* disable global interrupt mode */
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sc520_mmcr->picicr = 0x40;
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/* set all irqs to edge */
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sc520_mmcr->pic_mode[0] = 0x00;
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sc520_mmcr->pic_mode[1] = 0x00;
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sc520_mmcr->pic_mode[2] = 0x00;
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/* active low polarity on PIC interrupt pins,
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* active high polarity on all other irq pins */
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sc520_mmcr->intpinpol = 0x0000;
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/* set irq number mapping */
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sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */
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sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */
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sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */
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sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */
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sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */
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sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */
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sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */
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sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */
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sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */
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sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */
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sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */
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sc520_mmcr->ssimap = SC520_IRQ6; /* Set Synchronius serial INT to IRQ6*/
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sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */
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sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */
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sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */
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sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */
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sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */
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sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART1 INT to IRQ4 */
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sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */
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sc520_mmcr->gp_int_map[0] = SC520_IRQ7; /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
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sc520_mmcr->gp_int_map[1] = SC520_IRQ14; /* Set GPIRQ1 (CF IRQ) to IRQ14 */
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sc520_mmcr->gp_int_map[3] = SC520_IRQ5; /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
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sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disbale GIRQ4 ( IRR IRQ ) */
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sc520_mmcr->gp_int_map[5] = SC520_IRQ_DISABLED; /* disable GPIRQ5 */
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sc520_mmcr->gp_int_map[6] = SC520_IRQ_DISABLED; /* disable GPIRQ6 */
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sc520_mmcr->gp_int_map[7] = SC520_IRQ_DISABLED; /* disable GPIRQ7 */
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sc520_mmcr->gp_int_map[8] = SC520_IRQ_DISABLED; /* disable GPIRQ8 */
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sc520_mmcr->gp_int_map[9] = SC520_IRQ_DISABLED; /* disable GPIRQ9 */
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sc520_mmcr->gp_int_map[2] = SC520_IRQ_DISABLED; /* disable GPIRQ2 */
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sc520_mmcr->gp_int_map[10] = SC520_IRQ_DISABLED; /* disable GPIRQ10 */
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sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */
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sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */
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}
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/* set up the ISA bus timing and system address mappings */
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static void bus_init(void)
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{
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/* versions
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* 0 Hyglo versions 0.95 and 0.96 (large baords)
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* ?? Hyglo version 0.97 (small board)
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* 10 Spunk board
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*/
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int version = sc520_mmcr->sysinfo;
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if (version) {
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/* set up the GP IO pins (for the Spunk board) */
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sc520_mmcr->piopfs31_16 = 0xfff0; /* set the GPIO pin function 31-16 reg */
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sc520_mmcr->piopfs15_0 = 0x000f; /* set the GPIO pin function 15-0 reg */
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sc520_mmcr->piodir31_16 = 0x000f; /* set the GPIO direction 31-16 reg */
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sc520_mmcr->piodir15_0 = 0x1ff0; /* set the GPIO direction 15-0 reg */
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sc520_mmcr->cspfs = 0xc0; /* set the CS pin function reg */
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sc520_mmcr->clksel = 0x70;
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sc520_mmcr->pioclr31_16 = 0x0003; /* reset SSI chip-selects */
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sc520_mmcr->pioset31_16 = 0x000c;
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} else {
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/* set up the GP IO pins (for the Hyglo board) */
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sc520_mmcr->piopfs31_16 = 0xffc0; /* set the GPIO pin function 31-16 reg */
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sc520_mmcr->piopfs15_0 = 0x1e7f; /* set the GPIO pin function 15-0 reg */
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sc520_mmcr->piodir31_16 = 0x003f; /* set the GPIO direction 31-16 reg */
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sc520_mmcr->piodir15_0 = 0xe180; /* set the GPIO direction 15-0 reg */
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sc520_mmcr->cspfs = 0x00; /* set the CS pin function reg */
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sc520_mmcr->clksel = 0x70;
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sc520_mmcr->pioclr15_0 = 0x0180; /* reset SSI chip-selects */
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}
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sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */
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sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */
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sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */
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sc520_mmcr->gprdw = 3; /* set the RD pulse width */
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sc520_mmcr->gprdoff = 1; /* set the GP RD offset */
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sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */
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sc520_mmcr->gpwroff = 1; /* set the GP WR offset */
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sc520_mmcr->bootcsctl = 0x0407; /* set up timing of BOOTCS */
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/* adjust the memory map:
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* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
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* and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
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* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
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/* bootcs */
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sc520_mmcr->par[12] = 0x8bffe800;
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/* IDE0 = GPCS6 1f0-1f7 */
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sc520_mmcr->par[3] = 0x380801f0;
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/* IDE1 = GPCS7 3f6 */
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sc520_mmcr->par[4] = 0x3c0003f6;
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asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
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sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
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}
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/* par usage:
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* PAR0 (legacy_video)
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* PAR1 (PCI ROM mapping)
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* PAR2
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* PAR3 IDE
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* PAR4 IDE
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* PAR5 (legacy_video)
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* PAR6
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* PAR7 (legacy_video)
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* PAR8 (legacy_video)
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* PAR9 (legacy_video)
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* PAR10
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* PAR11 (ISAROM)
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* PAR12 BOOTCS
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* PAR13
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* PAR14
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* PAR15
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*/
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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init_sc520();
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bus_init();
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irq_init();
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/* max drive current on SDRAM */
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sc520_mmcr->dsctl = 0x0100;
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/* enter debug mode after next reset (only if jumper is also set) */
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sc520_mmcr->rescfg = 0x08;
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/* configure the software timer to 33.000MHz */
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sc520_mmcr->swtmrcfg = 1;
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gd->bus_clk = 33000000;
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return 0;
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}
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int dram_init(void)
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{
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init_sc520_dram();
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return 0;
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}
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void show_boot_progress(int val)
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{
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int version = sc520_mmcr->sysinfo;
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if (val < -32) val = -1; /* let things compatible */
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if (version == 0) {
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/* PIO31-PIO16 Data */
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sc520_mmcr->piodata31_16 = (sc520_mmcr->piodata31_16 & 0xffc0) | ((val&0x7e)>>1); /* 0x1f8 >> 3 */
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/* PIO0-PIO15 Data */
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sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0x1fff)| ((val&0x7)<<13);
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} else {
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/* newer boards use PIO4-PIO12 */
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/* PIO0-PIO15 Data */
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#if 0
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val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3);
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#else
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val = (val & 0x007) | ((val & 0x07e) << 2);
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#endif
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sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0xe00f) | ((val&0x01ff)<<4);
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}
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}
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int last_stage_init(void)
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{
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int version = sc520_mmcr->sysinfo;
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printf("Omicron Ceti SC520 Spunk revision %x\n", version);
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#if 0
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if (version) {
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int x, y;
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printf("eeprom probe %d\n", spi_eeprom_probe(1));
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spi_eeprom_read(1, 0, (u8*)&x, 2);
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spi_eeprom_read(1, 1, (u8*)&y, 2);
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printf("eeprom bytes %04x%04x\n", x, y);
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x ^= 0xffff;
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y ^= 0xffff;
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spi_eeprom_write(1, 0, (u8*)&x, 2);
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spi_eeprom_write(1, 1, (u8*)&y, 2);
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spi_eeprom_read(1, 0, (u8*)&x, 2);
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spi_eeprom_read(1, 1, (u8*)&y, 2);
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printf("eeprom bytes %04x%04x\n", x, y);
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} else {
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int x, y;
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printf("eeprom probe %d\n", mw_eeprom_probe(1));
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mw_eeprom_read(1, 0, (u8*)&x, 2);
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mw_eeprom_read(1, 1, (u8*)&y, 2);
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printf("eeprom bytes %04x%04x\n", x, y);
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x ^= 0xffff;
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y ^= 0xffff;
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mw_eeprom_write(1, 0, (u8*)&x, 2);
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mw_eeprom_write(1, 1, (u8*)&y, 2);
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mw_eeprom_read(1, 0, (u8*)&x, 2);
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mw_eeprom_read(1, 1, (u8*)&y, 2);
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printf("eeprom bytes %04x%04x\n", x, y);
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}
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#endif
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ds1722_probe(2);
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return 0;
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}
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void ssi_chip_select(int dev)
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{
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int version = sc520_mmcr->sysinfo;
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if (version) {
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/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
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switch (dev) {
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case 1: /* EEPROM */
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sc520_mmcr->pioclr31_16 = 0x0004;
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break;
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case 2: /* Temp Probe */
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sc520_mmcr->pioset31_16 = 0x0002;
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break;
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case 3: /* CAN */
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sc520_mmcr->pioclr31_16 = 0x0008;
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break;
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case 4: /* AUX */
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sc520_mmcr->pioset31_16 = 0x0001;
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break;
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case 0:
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sc520_mmcr->pioclr31_16 = 0x0003;
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sc520_mmcr->pioset31_16 = 0x000c;
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break;
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default:
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printf("Illegal SSI device requested: %d\n", dev);
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}
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} else {
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/* Globox board: Both EEPROM and TEMP are active-high */
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switch (dev) {
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case 1: /* EEPROM */
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sc520_mmcr->pioset15_0 = 0x0100;
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break;
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case 2: /* Temp Probe */
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sc520_mmcr->pioset15_0 = 0x0080;
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break;
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case 0:
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sc520_mmcr->pioclr15_0 = 0x0180;
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break;
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default:
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printf("Illegal SSI device requested: %d\n", dev);
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}
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}
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}
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void spi_eeprom_probe(int x)
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{
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}
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int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
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{
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return 0;
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}
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int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
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{
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return 0;
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}
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void mw_eeprom_probe(int x)
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{
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}
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int mw_eeprom_read(int x, int offset, uchar *buffer, int len)
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{
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return 0;
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}
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int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
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{
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return 0;
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}
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void spi_init_f(void)
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{
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sc520_mmcr->sysinfo ? spi_eeprom_probe(1) : mw_eeprom_probe(1);
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}
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ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
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{
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int offset;
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int i;
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offset = 0;
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for (i=0;i<alen;i++) {
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offset <<= 8;
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offset |= addr[i];
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}
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return sc520_mmcr->sysinfo ?
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spi_eeprom_read(1, offset, buffer, len) :
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mw_eeprom_read(1, offset, buffer, len);
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}
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ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
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{
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int offset;
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int i;
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offset = 0;
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for (i=0;i<alen;i++) {
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offset <<= 8;
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offset |= addr[i];
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}
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return sc520_mmcr->sysinfo ?
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spi_eeprom_write(1, offset, buffer, len) :
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mw_eeprom_write(1, offset, buffer, len);
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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