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e91df49fbb
Many (but not all) of Blackfin boards give -O2 option
to compile under lib/ directory.
That means lib/ should be speed-optimized,
whereas other parts should be size-optimized.
We want to keep the same behavior,
but do not want to parse board/*/config.mk again and again.
We've got no choice but to invent a new method.
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED, if it is enabled,
gives -O2 flag only for building under lib/ directory.
Dirty codes which I had marked as "FIX ME"
in board/${BOARD}/config.mk have been deleted.
Instead, CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED has been
defined in include/configs/${BOARD}.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
/*
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* U-boot - Configuration file for BF533 EZKIT board
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*/
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#ifndef __CONFIG_BF533_EZKIT_H__
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#define __CONFIG_BF533_EZKIT_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf533-0.3
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 27000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 22
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_SIZE 32
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/* Early EZKITs had 32megs, but later have 64megs */
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#if (CONFIG_MEM_SIZE == 64)
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# define CONFIG_MEM_ADD_WDTH 10
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#else
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# define CONFIG_MEM_ADD_WDTH 9
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#endif
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#define CONFIG_EBIU_SDRRC_VAL 0x398
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#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_SMC91111 1
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#define CONFIG_SMC91111_BASE 0x20310300
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#define SMC91111_EEPROM_INIT() \
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do { \
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bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
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bfin_write_FIO_FLAG_C(PF1); \
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bfin_write_FIO_FLAG_S(PF0); \
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SSYNC(); \
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} while (0)
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#define CONFIG_HOSTNAME bf533-ezkit
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 3
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#define CONFIG_SYS_MAX_FLASH_SECT 40
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR 0x20030000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define FLASH_TOT_SECT 40
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/*
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* I2C Settings
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*/
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#define CONFIG_SYS_I2C_SOFT
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#ifdef CONFIG_SYS_I2C_SOFT
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#define CONFIG_SYS_I2C
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#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
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#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
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#define CONFIG_SYS_I2C_SOFT_SPEED 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#endif
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/*
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* Misc Settings
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*/
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#define CONFIG_MISC_INIT_R
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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