Sean Anderson c41045411b Revert "riscv: Clear pending interrupts before enabling IPIs" ...

Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.

The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.

This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>

2020-09-30 08:54:52 +08:00

..

ax25

riscv: Rework riscv timer driver to only support S-mode

2020-09-30 08:54:45 +08:00

fu540

riscv: Rework riscv timer driver to only support S-mode

2020-09-30 08:54:45 +08:00

generic

riscv: Rework riscv timer driver to only support S-mode

2020-09-30 08:54:45 +08:00

cpu.c

riscv: Make SiFive HiFive Unleashed board boot again

2020-07-24 14:55:04 +08:00

Makefile

riscv: Move trap handler codes to mtrap.S

2018-12-18 09:56:27 +08:00

mtrap.S

riscv: Add option to print registers on exception

2020-02-10 14:51:08 +08:00

start.S

Revert "riscv: Clear pending interrupts before enabling IPIs"

2020-09-30 08:54:52 +08:00

u-boot-spl.lds

riscv: Add _image_binary_end for SPL

2020-06-04 09:44:08 +08:00

u-boot.lds

riscv: Fix breakage caused by linker relaxation

2020-02-10 14:50:53 +08:00