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* Supports dynamic panel configuration * Supports dynamic tv standard selection * Adds support for DSS register access through generic APIs * Incorporated DSS register access using structures. * DSS makefile update Previous discussions are here: http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
175 lines
4.7 KiB
C
175 lines
4.7 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* Referred to Linux Kernel DSS driver files for OMAP3 by
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* Tomi Valkeinen from drivers/video/omap2/dss/
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 and any
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* later version the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef DSS_H
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#define DSS_H
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/*
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* DSS Base Registers
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*/
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#define OMAP3_DSS_BASE 0x48050040
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#define OMAP3_DISPC_BASE 0x48050440
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#define OMAP3_VENC_BASE 0x48050C00
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/* DSS Registers */
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struct dss_regs {
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u32 control; /* 0x40 */
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u32 sdi_control; /* 0x44 */
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u32 pll_control; /* 0x48 */
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};
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/* DISPC Registers */
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struct dispc_regs {
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u32 control; /* 0x40 */
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u32 config; /* 0x44 */
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u32 reserve_2; /* 0x48 */
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u32 default_color0; /* 0x4C */
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u32 default_color1; /* 0x50 */
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u32 trans_color0; /* 0x54 */
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u32 trans_color1; /* 0x58 */
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u32 line_status; /* 0x5C */
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u32 line_number; /* 0x60 */
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u32 timing_h; /* 0x64 */
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u32 timing_v; /* 0x68 */
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u32 pol_freq; /* 0x6C */
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u32 divisor; /* 0x70 */
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u32 global_alpha; /* 0x74 */
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u32 size_dig; /* 0x78 */
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u32 size_lcd; /* 0x7C */
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};
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/* VENC Registers */
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struct venc_regs {
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u32 rev_id; /* 0x00 */
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u32 status; /* 0x04 */
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u32 f_control; /* 0x08 */
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u32 reserve_1; /* 0x0C */
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u32 vidout_ctrl; /* 0x10 */
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u32 sync_ctrl; /* 0x14 */
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u32 reserve_2; /* 0x18 */
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u32 llen; /* 0x1C */
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u32 flens; /* 0x20 */
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u32 hfltr_ctrl; /* 0x24 */
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u32 cc_carr_wss_carr; /* 0x28 */
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u32 c_phase; /* 0x2C */
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u32 gain_u; /* 0x30 */
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u32 gain_v; /* 0x34 */
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u32 gain_y; /* 0x38 */
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u32 black_level; /* 0x3C */
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u32 blank_level; /* 0x40 */
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u32 x_color; /* 0x44 */
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u32 m_control; /* 0x48 */
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u32 bstamp_wss_data; /* 0x4C */
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u32 s_carr; /* 0x50 */
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u32 line21; /* 0x54 */
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u32 ln_sel; /* 0x58 */
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u32 l21__wc_ctl; /* 0x5C */
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u32 htrigger_vtrigger; /* 0x60 */
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u32 savid__eavid; /* 0x64 */
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u32 flen__fal; /* 0x68 */
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u32 lal__phase_reset; /* 0x6C */
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u32 hs_int_start_stop_x; /* 0x70 */
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u32 hs_ext_start_stop_x; /* 0x74 */
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u32 vs_int_start_x; /* 0x78 */
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u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
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u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
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u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
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u32 vs_ext_stop_y; /* 0x88 */
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u32 reserve_3; /* 0x8C */
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u32 avid_start_stop_x; /* 0x90 */
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u32 avid_start_stop_y; /* 0x94 */
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u32 reserve_4; /* 0x98 */
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u32 reserve_5; /* 0x9C */
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u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
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u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
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u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
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u32 reserve_6; /* 0xAC */
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u32 tvdetgp_int_start_stop_x; /* 0xB0 */
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u32 tvdetgp_int_start_stop_y; /* 0xB4 */
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u32 gen_ctrl; /* 0xB8 */
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u32 reserve_7; /* 0xBC */
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u32 reserve_8; /* 0xC0 */
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u32 output_control; /* 0xC4 */
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u32 dac_b__dac_c; /* 0xC8 */
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u32 height_width; /* 0xCC */
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};
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/* Few Register Offsets */
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#define FRAME_MODE_SHIFT 1
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#define TFTSTN_SHIFT 3
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#define DATALINES_SHIFT 8
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/* Enabling Display controller */
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#define LCD_ENABLE 1
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#define DIG_ENABLE (1 << 1)
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#define GO_LCD (1 << 5)
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#define GO_DIG (1 << 6)
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#define GP_OUT0 (1 << 15)
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#define GP_OUT1 (1 << 16)
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#define DISPC_ENABLE (LCD_ENABLE | \
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DIG_ENABLE | \
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GO_LCD | \
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GO_DIG | \
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GP_OUT0| \
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GP_OUT1)
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/* Configure VENC DSS Params */
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#define VENC_CLK_ENABLE (1 << 3)
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#define DAC_DEMEN (1 << 4)
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#define DAC_POWERDN (1 << 5)
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#define VENC_OUT_SEL (1 << 6)
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#define DIG_LPP_SHIFT 16
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#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
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DAC_DEMEN | \
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DAC_POWERDN | \
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VENC_OUT_SEL)
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/*
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* Panel Configuration
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*/
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struct panel_config {
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u32 timing_h;
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u32 timing_v;
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u32 pol_freq;
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u32 divisor;
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u32 lcd_size;
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u32 panel_type;
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u32 data_lines;
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u32 load_mode;
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u32 panel_color;
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};
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/*
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* Generic DSS Functions
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*/
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void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
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u32 height, u32 width);
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void omap3_dss_panel_config(const struct panel_config *panel_cfg);
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void omap3_dss_enable(void);
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#endif /* DSS_H */
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