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84b6631038
Introduce Numonyx DDR timings and provide CONFIG_OMAP3_NUMONYX_DDR config options to allow for platform files to setup their timings. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Acked-by: Steve Sakoman <steve.sakoman@linaro.org> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
330 lines
9.5 KiB
C
330 lines
9.5 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _MEM_H_
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#define _MEM_H_
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#define CS0 0x0
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#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
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#ifndef __ASSEMBLY__
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enum {
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STACKED = 0,
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IP_DDR = 1,
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COMBO_DDR = 2,
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IP_SDR = 3,
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};
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#endif /* __ASSEMBLY__ */
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#define EARLY_INIT 1
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/* Slower full frequency range default timings for x32 operation*/
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#define SDRC_SHARING 0x00000100
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#define SDRC_MR_0_SDR 0x00000031
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#define DLL_OFFSET 0
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#define DLL_WRITEDDRCLKX2DIS 1
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#define DLL_ENADLL 1
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#define DLL_LOCKDLL 0
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#define DLL_DLLPHASE_72 0
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#define DLL_DLLPHASE_90 1
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/* rkw - need to find of 90/72 degree recommendation for speed like before */
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#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
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(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 18/6 = 3
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 72/6 = 12
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* ACTIMB
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* TCKE = 2
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* XSR = 120/6 = 20
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*/
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#define INFINEON_TDAL_165 6
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#define INFINEON_TDPL_165 3
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#define INFINEON_TRRD_165 2
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#define INFINEON_TRCD_165 3
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#define INFINEON_TRP_165 3
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#define INFINEON_TRAS_165 7
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#define INFINEON_TRC_165 10
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#define INFINEON_TRFC_165 12
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#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
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(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
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(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
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(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
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(INFINEON_TDAL_165))
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#define INFINEON_TWTR_165 1
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#define INFINEON_TCKE_165 2
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#define INFINEON_TXP_165 2
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#define INFINEON_XSR_165 20
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#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
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(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
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(INFINEON_TWTR_165 << 16))
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/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 18/6 = 3
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 125/6 = 21
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* ACTIMB
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* TWTR = 1
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* TCKE = 1
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* TXSR = 138/6 = 23
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* TXP = 25/6 = 4.1 ~5
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*/
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#define MICRON_TDAL_165 6
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#define MICRON_TDPL_165 3
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#define MICRON_TRRD_165 2
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#define MICRON_TRCD_165 3
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#define MICRON_TRP_165 3
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#define MICRON_TRAS_165 7
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#define MICRON_TRC_165 10
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#define MICRON_TRFC_165 21
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#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
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(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
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(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
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(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
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(MICRON_TDAL_165))
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#define MICRON_TWTR_165 1
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#define MICRON_TCKE_165 1
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#define MICRON_XSR_165 23
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#define MICRON_TXP_165 5
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#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
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(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
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(MICRON_TWTR_165 << 16))
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/*
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* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
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* ACTIMA
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
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* TDPL (Twr) = 15/6 = 2.5 -> 3
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* TRRD = 12/6 = 2
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* TRCD = 22.5/6 = 3.75 -> 4
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* TRP = 18/6 = 3
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* TRAS = 42/6 = 7
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* TRC = 60/6 = 10
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* TRFC = 140/6 = 23.3 -> 24
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* ACTIMB
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* TWTR = 2
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* TCKE = 2
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* TXSR = 200/6 = 33.3 -> 34
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* TXP = 1.0 + 1.1 = 2.1 -> 3
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*/
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#define NUMONYX_TDAL_165 6
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#define NUMONYX_TDPL_165 3
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#define NUMONYX_TRRD_165 2
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#define NUMONYX_TRCD_165 4
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#define NUMONYX_TRP_165 3
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#define NUMONYX_TRAS_165 7
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#define NUMONYX_TRC_165 10
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#define NUMONYX_TRFC_165 24
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#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
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(NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
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(NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
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(NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
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(NUMONYX_TDAL_165))
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#define NUMONYX_TWTR_165 2
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#define NUMONYX_TCKE_165 2
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#define NUMONYX_TXP_165 3
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#define NUMONYX_XSR_165 34
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#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
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(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
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(NUMONYX_TWTR_165 << 16))
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#ifdef CONFIG_OMAP3_INFINEON_DDR
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#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
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#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
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#endif
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#ifdef CONFIG_OMAP3_MICRON_DDR
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#define V_ACTIMA_165 MICRON_V_ACTIMA_165
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#define V_ACTIMB_165 MICRON_V_ACTIMB_165
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#endif
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#ifdef CONFIG_OMAP3_NUMONYX_DDR
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#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
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#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
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#endif
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#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
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#error "Please choose the right DDR type in config header"
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#endif
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/*
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* GPMC settings -
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* Definitions is as per the following format
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* #define <PART>_GPMC_CONFIG<x> <value>
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* Where:
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* PART is the part name e.g. STNOR - Intel Strata Flash
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* x is GPMC config registers from 1 to 6 (there will be 6 macros)
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* Value is corresponding value
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*
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* For every valid PRCM configuration there should be only one definition of
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* the same. if values are independent of the board, this definition will be
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* present in this file if values are dependent on the board, then this should
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* go into corresponding mem-boardName.h file
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*
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* Currently valid part Names are (PART):
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* STNOR - Intel Strata Flash
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* SMNAND - Samsung NAND
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* MPDB - H4 MPDB board
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* SBNOR - Sibley NOR
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* MNAND - Micron Large page x16 NAND
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* ONNAND - Samsung One NAND
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*
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* include/configs/file.h contains the defn - for all CS we are interested
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* #define OMAP34XX_GPMC_CSx PART
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* #define OMAP34XX_GPMC_CSx_SIZE Size
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* #define OMAP34XX_GPMC_CSx_MAP Map
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* Where:
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* x - CS number
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* PART - Part Name as defined above
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* SIZE - how big is the mapping to be
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* GPMC_SIZE_128M - 0x8
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* GPMC_SIZE_64M - 0xC
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* GPMC_SIZE_32M - 0xE
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* GPMC_SIZE_16M - 0xF
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* MAP - Map this CS to which address(GPMC address space)- Absolute address
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* >>24 before being used.
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*/
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#define GPMC_SIZE_128M 0x8
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#define GPMC_SIZE_64M 0xC
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#define GPMC_SIZE_32M 0xE
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#define GPMC_SIZE_16M 0xF
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#define SMNAND_GPMC_CONFIG1 0x00000800
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#define SMNAND_GPMC_CONFIG2 0x00141400
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#define SMNAND_GPMC_CONFIG3 0x00141400
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#define SMNAND_GPMC_CONFIG4 0x0F010F01
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#define SMNAND_GPMC_CONFIG5 0x010C1414
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#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
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#define SMNAND_GPMC_CONFIG7 0x00000C44
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#define M_NAND_GPMC_CONFIG1 0x00001800
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#define M_NAND_GPMC_CONFIG2 0x00141400
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#define M_NAND_GPMC_CONFIG3 0x00141400
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#define M_NAND_GPMC_CONFIG4 0x0F010F01
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#define M_NAND_GPMC_CONFIG5 0x010C1414
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#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
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#define M_NAND_GPMC_CONFIG7 0x00000C44
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#define STNOR_GPMC_CONFIG1 0x3
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#define STNOR_GPMC_CONFIG2 0x00151501
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#define STNOR_GPMC_CONFIG3 0x00060602
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#define STNOR_GPMC_CONFIG4 0x11091109
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#define STNOR_GPMC_CONFIG5 0x01141F1F
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#define STNOR_GPMC_CONFIG6 0x000004c4
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#define SIBNOR_GPMC_CONFIG1 0x1200
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#define SIBNOR_GPMC_CONFIG2 0x001f1f00
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#define SIBNOR_GPMC_CONFIG3 0x00080802
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#define SIBNOR_GPMC_CONFIG4 0x1C091C09
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#define SIBNOR_GPMC_CONFIG5 0x01131F1F
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#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
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#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
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#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
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#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
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#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
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#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
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#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
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#define MPDB_GPMC_CONFIG1 0x00011000
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#define MPDB_GPMC_CONFIG2 0x001f1f01
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#define MPDB_GPMC_CONFIG3 0x00080803
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#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
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#define MPDB_GPMC_CONFIG5 0x041f1F1F
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#define MPDB_GPMC_CONFIG6 0x1F0F04C4
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#define P2_GPMC_CONFIG1 0x0
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#define P2_GPMC_CONFIG2 0x0
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#define P2_GPMC_CONFIG3 0x0
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#define P2_GPMC_CONFIG4 0x0
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#define P2_GPMC_CONFIG5 0x0
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#define P2_GPMC_CONFIG6 0x0
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#define ONENAND_GPMC_CONFIG1 0x00001200
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#define ONENAND_GPMC_CONFIG2 0x000F0F01
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#define ONENAND_GPMC_CONFIG3 0x00030301
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#define ONENAND_GPMC_CONFIG4 0x0F040F04
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#define ONENAND_GPMC_CONFIG5 0x010F1010
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#define ONENAND_GPMC_CONFIG6 0x1F060000
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#define NET_GPMC_CONFIG1 0x00001000
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#define NET_GPMC_CONFIG2 0x001e1e01
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#define NET_GPMC_CONFIG3 0x00080300
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#define NET_GPMC_CONFIG4 0x1c091c09
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#define NET_GPMC_CONFIG5 0x04181f1f
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#define NET_GPMC_CONFIG6 0x00000FCF
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#define NET_GPMC_CONFIG7 0x00000f6c
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/* max number of GPMC Chip Selects */
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#define GPMC_MAX_CS 8
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/* max number of GPMC regs */
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#define GPMC_MAX_REG 7
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#define PISMO1_NOR 1
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#define PISMO1_NAND 2
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#define PISMO2_CS0 3
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#define PISMO2_CS1 4
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#define PISMO1_ONENAND 5
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#define DBG_MPDB 6
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#define PISMO2_NAND_CS0 7
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#define PISMO2_NAND_CS1 8
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/* make it readable for the gpmc_init */
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#define PISMO1_NOR_BASE FLASH_BASE
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#define PISMO1_NAND_BASE NAND_BASE
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#define PISMO2_CS0_BASE PISMO2_MAP1
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#define PISMO1_ONEN_BASE ONENAND_MAP
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#define DBG_MPDB_BASE DEBUG_BASE
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#ifndef __ASSEMBLY__
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/* Function prototypes */
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void mem_init(void);
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u32 is_mem_sdr(void);
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u32 mem_ok(u32 cs);
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u32 get_sdr_cs_size(u32);
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u32 get_sdr_cs_offset(u32);
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#endif /* __ASSEMBLY__ */
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#endif /* endif _MEM_H_ */
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