Paul Burton d608254b0a MIPS: Clear hazard between TagLo writes & cache ops ...

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

2016-09-21 15:04:04 +02:00

..

cpu

MIPS: Ensure Config.K0=2 applies before any memory accesses

2016-09-21 15:04:04 +02:00

dts

mips: xilfpga: Add device tree files

2016-09-21 14:55:14 +02:00

include/asm

MIPS: Join the coherent domain when a CM is present

2016-09-21 15:04:04 +02:00

lib

MIPS: Clear hazard between TagLo writes & cache ops

2016-09-21 15:04:04 +02:00

mach-ath79

MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init

2016-09-21 15:04:04 +02:00

mach-au1x00

net: mii: Use spatch to update miiphy_register

2016-08-15 15:26:33 -05:00

mach-pic32

clk: convert API to match reset/mailbox style

2016-06-19 17:05:55 -06:00

config.mk

MIPS: provide a default u-boot-spl.lds

2016-05-31 09:38:11 +02:00

Kconfig

MIPS: Malta: Enable CM & L2 support

2016-09-21 15:04:04 +02:00

Makefile

MIPS: add tune for MIPS 34kc

2016-05-31 09:38:11 +02:00