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	MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family and used a common MPU's region config. Only one exception for STM32H7 which doesn't have device area located at 0xA000 0000. For STM32F4, configure_clocks() need to be moved from arch_cpu_init() to board_early_init_f(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
		
			
				
	
	
		
			57 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			57 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
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 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m_mpu.h>
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int arch_cpu_init(void)
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{
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	int i;
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	struct mpu_region_config stm32_region_config[] = {
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		/*
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		 * Make all 4GB cacheable & executable. We are overriding it
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		 * with next region for any requirement. e.g. below region1,
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		 * 2 etc.
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		 * In other words, the area not coming in following
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		 * regions configuration is the one configured here in region_0
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		 * (cacheable & executable).
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		 */
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		{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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		O_I_WB_RD_WR_ALLOC, REGION_4GB },
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		/* armv7m code area */
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		{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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		STRONG_ORDER, REGION_512MB },
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		/* Device area : Not executable */
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		{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
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		DEVICE_NON_SHARED, REGION_512MB },
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		/*
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		 * Armv7m fixed configuration: strongly ordered & not
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		 * executable, not cacheable
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		 */
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		{ 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
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		STRONG_ORDER, REGION_512MB },
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#if !defined(CONFIG_STM32H7)
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		/* Device area : Not executable */
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		{ 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
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		DEVICE_NON_SHARED, REGION_512MB },
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#endif
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	};
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	disable_mpu();
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	for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
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		mpu_config(&stm32_region_config[i]);
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	enable_mpu();
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	return 0;
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}
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