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645ee3c25d
Add support for F1C100s internal dram controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
44 lines
1.0 KiB
C
44 lines
1.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* DRAM init helper functions
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*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*/
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#include <common.h>
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#include <time.h>
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#include <asm/barriers.h>
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#include <asm/io.h>
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#include <asm/arch/dram.h>
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/*
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* Wait up to 1s for value to be set in given part of reg.
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*/
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void mctl_await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo)
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panic("Timeout initialising DRAM\n");
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}
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}
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/*
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* Test if memory at offset offset matches memory at begin of DRAM
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*
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* Note: dsb() is not available on ARMv5 in Thumb mode
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*/
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#ifndef CONFIG_MACH_SUNIV
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bool mctl_mem_matches(u32 offset)
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{
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/* Try to write different values to RAM at two addresses */
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
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dsb();
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/* Check if the same value is actually observed when reading back */
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return readl(CONFIG_SYS_SDRAM_BASE) ==
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readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
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}
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#endif
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